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drm/i915/dsb: Introduce intel_dsb_exec_time_us()

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Pull the magic 20 usec DSB execution deadline into
intel_dsb_arm_exec_time_us(), and also add its counterpart
for the non-arming register write section. For the non-arming
part we'll just throw in a random 80 usec for now so the total
is 100usec. The total exec time will be needed by the upcoming
flip queue code.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-4-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
2025-06-12 17:50:15 +03:00
parent 7e151f53fd
commit ee14e265e1
2 changed files with 25 additions and 2 deletions
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26
drivers/gpu/drm/i915/display/intel_dsb.c
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@@ -685,14 +685,36 @@ static u32 dsb_error_int_en(struct intel_display *display)
return errors;
}
/*
* FIXME calibrate these sensibly, ideally compute based on
* the number of regisetrs to be written. But that requires
* measuring the actual DSB execution speed on each platform
* (and the speed also depends on CDCLK and memory clock)...
*/
static int intel_dsb_noarm_exec_time_us(void)
{
return 80;
}
static int intel_dsb_arm_exec_time_us(void)
{
return 20;
}
int intel_dsb_exec_time_us(void)
{
return intel_dsb_noarm_exec_time_us() +
intel_dsb_arm_exec_time_us();
}
void intel_dsb_vblank_evade(struct intel_atomic_state *state,
struct intel_dsb *dsb)
{
struct intel_crtc *crtc = dsb->crtc;
const struct intel_crtc_state *crtc_state =
intel_pre_commit_crtc_state(state, crtc);
/* FIXME calibrate sensibly */
int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20);
int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
intel_dsb_arm_exec_time_us());
int start, end;
/*