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PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode

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Calibrate 'Pipe to Universal PHY(UPHY)' (P2U) for the Endpoint controller
to request UPHY PLL rate change to 2.5GT/s (Gen 1) during initialization.
This helps to reset stale PLL state from the previous bad link state.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://patch.msgid.link/20260324191000.1095768-3-mmaddireddy@nvidia.com
This commit is contained in:
Vidya Sagar
2026-03-25 00:39:53 +05:30
committed by Bjorn Helgaas
parent 01d36261ae
commit f50e0c7d57
1 changed files with 3 additions and 0 deletions
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3
drivers/pci/controller/dwc/pcie-tegra194.c
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@@ -1072,6 +1072,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
ret = phy_power_on(pcie->phys[i]);
if (ret < 0)
goto phy_exit;
if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
phy_calibrate(pcie->phys[i]);
}
return 0;