bybrooklyn/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-04-18 14:53:58 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amdgpu: fix mes packet params issue when flush hdp.

Browse Source 
v4:
use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for
gfx9 through gfx12.

v3:
Unify the get_ref_and_mask function in amdgpu_gfx_funcs,
to support both GFX11 and earlier generations

v2:
place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring,
since this function only assigns the cp entry.

v1:
both gfx ring and mes ring use cp0 to flush hdp, cause conflict.

use function get_ref_and_mask to assign the cp entry.
reassign mes to use cp8 instead.

Signed-off-by: chong li <chongli2@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
chong li
2025-11-28 10:51:51 +08:00
committed by Alex Deucher
parent e26e4225ae
commit f9f3240018
10 changed files with 160 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
View File

@@ -1197,6 +1197,40 @@ failed_kiq_write:
dev_err(adev->dev, "failed to write reg:%x\n", reg);
}
void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring,
uint32_t *hdp_flush_mask, uint32_t *reg_mem_engine)
{
if (!ring || !hdp_flush_mask || !reg_mem_engine) {
DRM_INFO("%s:invalid params\n", __func__);
return;
}
const struct nbio_hdp_flush_reg *nbio_hf_reg = ring->adev->nbio.hdp_flush_reg;
switch (ring->funcs->type) {
case AMDGPU_RING_TYPE_GFX:
*hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
*reg_mem_engine = 1; /* pfp */
break;
case AMDGPU_RING_TYPE_COMPUTE:
*hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
*reg_mem_engine = 0;
break;
case AMDGPU_RING_TYPE_MES:
*hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp8;
*reg_mem_engine = 0;
break;
case AMDGPU_RING_TYPE_KIQ:
*hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp9;
*reg_mem_engine = 0;
break;
default:
DRM_ERROR("%s:unsupported ring type %d\n", __func__, ring->funcs->type);
return;
}
}
int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev)
{
signed long r, cnt = 0;