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drm/amdgpu: fix mes packet params issue when flush hdp.
v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li <chongli2@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -358,6 +358,8 @@ struct amdgpu_gfx_funcs {
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int num_xccs_per_xcp);
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int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);
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int (*get_xccs_per_xcp)(struct amdgpu_device *adev);
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void (*get_hdp_flush_mask)(struct amdgpu_ring *ring,
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uint32_t *ref_and_mask, uint32_t *reg_mem_engine);
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};
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struct sq_work {
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@@ -617,6 +619,8 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);
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void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);
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void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring,
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uint32_t *ref_and_mask, uint32_t *reg_mem_engine);
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int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev);
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int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
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void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
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