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drm/amdgpu: fix mes packet params issue when flush hdp.

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v4:
use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for
gfx9 through gfx12.

v3:
Unify the get_ref_and_mask function in amdgpu_gfx_funcs,
to support both GFX11 and earlier generations

v2:
place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring,
since this function only assigns the cp entry.

v1:
both gfx ring and mes ring use cp0 to flush hdp, cause conflict.

use function get_ref_and_mask to assign the cp entry.
reassign mes to use cp8 instead.

Signed-off-by: chong li <chongli2@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
chong li
2025-11-28 10:51:51 +08:00
committed by Alex Deucher
parent e26e4225ae
commit f9f3240018
10 changed files with 160 additions and 114 deletions
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13
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
View File

@@ -557,11 +557,20 @@ error:
int amdgpu_mes_hdp_flush(struct amdgpu_device *adev)
{
uint32_t hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask;
uint32_t hdp_flush_req_offset, hdp_flush_done_offset;
struct amdgpu_ring *mes_ring;
uint32_t ref_and_mask = 0, reg_mem_engine = 0;
if (!adev->gfx.funcs->get_hdp_flush_mask) {
dev_err(adev->dev, "mes hdp flush is not supported.\n");
return -EINVAL;
}
mes_ring = &adev->mes.ring[0];
hdp_flush_req_offset = adev->nbio.funcs->get_hdp_flush_req_offset(adev);
hdp_flush_done_offset = adev->nbio.funcs->get_hdp_flush_done_offset(adev);
ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0;
adev->gfx.funcs->get_hdp_flush_mask(mes_ring, &ref_and_mask, &reg_mem_engine);
return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset,
ref_and_mask, ref_and_mask, 0);