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drm/msm: resync generated headers
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@@ -42,27 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum mdp4_bpc {
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BPC1 = 0,
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BPC5 = 1,
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BPC6 = 2,
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BPC8 = 3,
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};
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enum mdp4_bpc_alpha {
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BPC1A = 0,
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BPC4A = 1,
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BPC6A = 2,
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BPC8A = 3,
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};
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enum mdp4_alpha_type {
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FG_CONST = 0,
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BG_CONST = 1,
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FG_PIXEL = 2,
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BG_PIXEL = 3,
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};
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enum mdp4_pipe {
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VG1 = 0,
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VG2 = 1,
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@@ -79,15 +60,6 @@ enum mdp4_mixer {
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MIXER2 = 2,
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};
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enum mdp4_mixer_stage_id {
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STAGE_UNUSED = 0,
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STAGE_BASE = 1,
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STAGE0 = 2,
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STAGE1 = 3,
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STAGE2 = 4,
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STAGE3 = 5,
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};
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enum mdp4_intf {
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INTF_LCDC_DTV = 0,
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INTF_DSI_VIDEO = 1,
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@@ -194,56 +166,56 @@ static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
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#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
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}
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@@ -254,56 +226,56 @@ static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id va
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#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
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#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
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#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
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#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
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#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
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#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
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#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
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#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
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}
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@@ -369,7 +341,7 @@ static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x
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static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
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#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
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#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
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static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
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static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
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{
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return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
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}
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@@ -377,7 +349,7 @@ static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
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#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
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#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
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#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
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static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val)
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static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
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{
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return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
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}
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@@ -472,19 +444,19 @@ static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __of
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static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
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#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
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#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
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static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val)
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static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
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{
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return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
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}
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#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
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#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
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static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val)
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static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
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{
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return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
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}
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#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
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#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
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static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val)
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static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
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{
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return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
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}
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@@ -710,25 +682,25 @@ static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
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static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
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#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
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#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val)
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
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{
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return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
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}
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#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
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#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val)
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
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{
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return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
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}
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#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
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#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val)
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
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{
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return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
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}
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#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
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#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val)
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static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
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||||
{
|
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return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
|
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}
|
||||
|
||||
Reference in New Issue
Block a user