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docs: Downgrade arm64 & riscv from titles to comment

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Remove the title string ("====") from under arm64 & riscv and move them
to a commment under the perf_user_access sysctl. They are explanations,
*not* sysctls themselves

This effectively removes these two strings from appearing as not
implemented when the check-sysctl-docs script is run

Signed-off-by: Joel Granados <joel.granados@kernel.org>
This commit is contained in:
Joel Granados
2025-07-01 10:39:27 +02:00
parent 999aab7f56
commit ffc137c5c1
1 changed files with 14 additions and 18 deletions
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32
Documentation/admin-guide/sysctl/kernel.rst
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@@ -1014,30 +1014,26 @@ perf_user_access (arm64 and riscv only)
Controls user space access for reading perf event counters.
arm64
=====
* for arm64
The default value is 0 (access disabled).
The default value is 0 (access disabled).
When set to 1, user space can read performance monitor counter registers
directly.
When set to 1, user space can read performance monitor counter registers
directly.
See Documentation/arch/arm64/perf.rst for more information.
See Documentation/arch/arm64/perf.rst for more information.
* for riscv
When set to 0, user space access is disabled.
riscv
=====
The default value is 1, user space can read performance monitor counter
registers through perf, any direct access without perf intervention will trigger
an illegal instruction.
When set to 0, user space access is disabled.
When set to 2, which enables legacy mode (user space has direct access to cycle
and insret CSRs only). Note that this legacy value is deprecated and will be
removed once all user space applications are fixed.
The default value is 1, user space can read performance monitor counter
registers through perf, any direct access without perf intervention will trigger
an illegal instruction.
When set to 2, which enables legacy mode (user space has direct access to cycle
and insret CSRs only). Note that this legacy value is deprecated and will be
removed once all user space applications are fixed.
Note that the time CSR is always directly accessible to all modes.
Note that the time CSR is always directly accessible to all modes.
pid_max
=======