Krzysztof Kozlowski
667facc400
dt-bindings: PCI: qcom,pcie-sm8450: Add missing required power-domains and resets
...
Commit 88c9b3af4e88c9b3af4ekrzysztof.kozlowski@linaro.org >
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251030-dt-bindings-pci-qcom-fixes-power-domains-v2-7-28c1f11599fe@linaro.org
2025-11-17 18:32:58 +05:30
Manivannan Sadhasivam
e3d7fda088
dt-bindings: PCI: Update the email address for Manivannan Sadhasivam
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My linaro email id is no longer active. So switch to kernel.org one.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com >
Link: https://patch.msgid.link/20251010-pci-binding-v1-1-947c004b5699@oss.qualcomm.com
Acked-by: Rob Herring (Arm) <robh@kernel.org >
2025-10-26 21:26:34 +05:30
Qiang Yu
39a06b55df
dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml
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OPP table is a generic property that is also required by other Qcom
platforms.
Hence move this property to qcom,pcie-common.yaml so that PCIe on other
Qcom platforms is able to adjust power domain performance state and ICC
peak bandwidth according to the given PCIe generation speed and link
width.
Link: https://lore.kernel.org/r/20241101030902.579789-2-quic_qianyu@quicinc.com
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com >
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org >
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
2024-11-03 20:12:41 +00:00
Manivannan Sadhasivam
6efd853303
dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
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Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPU. This interrupt can be used by the device driver to
identify events such as PCIe link specific events, safety events, etc...
Hence, document it in the binding along with the existing MSI interrupts.
Though adding a new interrupt will break the ABI, it is required to
accurately describe the hardware.
Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-10-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
2024-09-01 08:12:26 +00:00
Krishna chaitanya chundru
bdf8e4d5d6
dt-bindings: PCI: qcom: Add OPP table
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PCIe needs to choose the appropriate performance state of RPMh power
domain based on the PCIe gen speed.
Adding the Operating Performance Points table allows to adjust power
domain performance state and ICC peak bw, depending on the PCIe data
rate and link width.
Link: https://lore.kernel.org/linux-pci/20240619-opp_support-v15-2-aa769a2173a3@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com >
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org >
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
2024-07-04 14:46:09 +00:00
Krzysztof Kozlowski
88c9b3af4e
dt-bindings: PCI: qcom,pcie-sm8450: Move SM8450 to dedicated schema
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Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.
This creates equivalent schema file, except:
- Missing required compatible which is actually redundant.
- Expecting eight MSI interrupts, instead of only one, which was
incomplete hardware description.
Link: https://lore.kernel.org/linux-pci/20240126-dt-bindings-pci-qcom-split-v3-2-f23cda4d74c0@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Rob Herring <robh@kernel.org >
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
2024-02-23 11:33:22 +00:00
