Commit Graph

11 Commits

Author SHA1 Message Date
Relja Vojvodic
8aa5aff2bf drm/amd/display: Refactor dccg401_get_other_enable_symclk_fe
[WHY]
Function was used to check the number of FEs connected to the current BE.
This was then used to determine if the symclk could be disabled, if all
FEs were disconnected. However, the function would skip over the primary
FE and return 0 when the primary FE was still connected. This caused black
screens on driver disable with an MST daisy chain hooked up.

[HOW]
Refactored the function to correctly return the number of FEs connected to
the input BE. Also renamed it for clarity.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-27 17:10:35 -04:00
Alex Hung
d281b77426 drm/amd/display: Fix incorrect size calculation for loop in dcn401
[WHY]
fe_clk_en and be_clk_sel have size of 4 but sizeof(fe_clk_en) has
byte size 16 which is lager than the array size.

[HOW]
Use ARRAY_SIZE for calculating size.

This fixes 2 OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-14 16:17:17 -04:00
Chris Park
d3d996ec89 drm/amd/display: Avoid programming DTO if Refclk is 0
[Why]
Reference clock, either DPREFCLK or DTBCLK can be a value of 0
which then will encounter division by 0.

[How]
Avoid further calculation and programming if refclk is not
populated.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-14 16:17:15 -04:00
yi-lchen
975507d73c drm/amd/display: Keep VBios pixel rate div setting until next mode set
[why]
Vbios & Driver have difference pixel rate div policy.
When enabling fast boot & performing blank & unblank w/o timing setting,
pixel clock & pixel rate dividor are not match.
It would cause too high pixel reate and eDP would be black screen.

[How]
We would keep pixel rate div setting by Vbios until next timing setting.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: yi-lchen <yi-lchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-05 11:04:50 -04:00
Alex Hung
70bb97d95f drm/amd/display: Adjust incorrect indentations and spaces
This fixes indentations and adjust spaces for better readability and
code styles.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-20 16:19:34 -04:00
Wenjing Liu
872c0de315 drm/amd/display: Add missing enable and disable symclk_se functions for dcn401
The functions are missing. These two functions are required to support
MST.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-20 16:19:34 -04:00
Alex Hung
56116dc7a9 Revert "drm/amd/display: Enable SYMCLK gating in DCCG"
This reverts commit c49e44ede5.

This causes regression on DP link layer test.

Reported-by: Mark Broadworth <Mark.Broadworth@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13 15:48:45 -04:00
Daniel Miess
c49e44ede5 drm/amd/display: Enable SYMCLK gating in DCCG
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13 15:47:08 -04:00
Revalla Hari Krishna
30c646afea drm/amd/display: Refactor DCN401 DCCG into component directory
[WHY]
Clean up the code that requires dccg to be in its own component.

[HOW]
Move all files under newly created dccg dir and fix the makefiles.

Acked-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Revalla Hari Krishna <Harikrishna.Revalla@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13 15:46:35 -04:00
Alex Hung
3941a3aa4b drm/amd/display: Fix incorrect size calculation for loop
[WHY]
fe_clk_en has size of 5 but sizeof(fe_clk_en) has byte size 20 which is
lager than the array size.

[HOW]
Divide byte size 20 by its element size.

This fixes 2 OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-02 16:18:16 -04:00
Revalla Hari Krishna
0a8d25285f drm/amd/display: Refactor DCCG into component folder
[why]
cleaning up the code refactor requires dccg to be in its own component.

[how]
move all files under newly created dccg folder and fixing the
makefiles.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Revalla Hari Krishna <harikrishna.revalla@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-02 16:18:16 -04:00