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27 Commits

Author SHA1 Message Date
Biju Das
307ca5cf47 ARM: dts: r8a77470: Add HSUSB device nodes 
Define the r8a77470 generic part of the HSUSB0/1 device nodes.

Currently the renesas_usbhs driver doesn't handle multiple phys and we
don't have a proper hardware to validate such driver changes.

So for hsusb1 it is assumed that usbphy0 will be enabled by either
channel0 host or device.

In future, if any boards support hsusb1, we will need to add multiple phy
support in the renesas_usbhs driver and override the board dts to enable
the same.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:24:35 +02:00
Biju Das
ce5940798c ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) device 
Define the r8a77470 generic part of the USB2.0 Host Controller device
nodes (ehci[01]/ohci[01]).

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:21:55 +02:00
Biju Das
1a675db440 ARM: dts: r8a77470: Add USB PHY DT support 
Define the r8a77470 generic part of the USB PHY device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:17:42 +02:00
Cao Van Dong
1631b58c7e ARM: dts: r8a77470: Add VIN support 
Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 14:06:25 +02:00
Cao Van Dong
3d59e55ef8 ARM: dts: r8a77470: Add PWM support 
Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the
RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 13:59:09 +02:00
Cao Van Dong
f408170d18 ARM: dts: r8a77470: Add HSCIF support 
Add hscif{0|1|2} nodes to dtsi for HSCIF support on the
RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-04-12 13:53:07 +02:00
Fabrizio Castro
4ec778fb0f ARM: dts: r8a77470: Add DU support 
This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2019-03-25 11:56:40 +01:00
Fabrizio Castro
b6239d4219 ARM: dts: r8a77470: Add QSPI support 
Add QSPI[01] support to the RZ/G1C SoC specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:29 +01:00
Biju Das
8129890823 ARM: dts: r8a77470: Add CMT SoC specific support 
Add CMT[01] support to r8a77470 SoC DT.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:27 +01:00
Biju Das
92c3ccd9b8 ARM: dts: r8a77470: Add USB-DMAC device nodes 
This patch adds USB DMAC nodes.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:26 +01:00
Biju Das
dc7bf8795d ARM: dts: r8a77470: Add watchdog support to SoC dtsi 
This patch adds watchdog support to the r8a77470 SoC dtsi.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[simon: moved node to preserve sort order]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:25 +01:00
Fabrizio Castro
0485da7880 ARM: dts: r8a77470: Add SDHI1 support 
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a.
r8a77470) is compatible with the R-Car Gen3 ones, its OF
compatibility is restricted to the SoC specific compatible
string to avoid confusion, as from a more generic perspective
the RZ/G1C is sharing the most similarities with the R-Car
Gen2 family of SoCs, and there is a combination of R-Car
Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP
on this specific chip.
This patch adds the SoC specific part of SDHI1 support, and
since SDHI1 comes with internal DMA, its DT node looks fairly
different from SDHI0 and SDHI2.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:22 +01:00
Fabrizio Castro
15aa5a95e8 ARM: dts: r8a77470: Add SDHI0 support 
RZ/G1C comes with two different types of IP for the SDHI
interfaces, SDHI0 and SDHI2 share the same IP type, and
such an IP is also compatible with the one found in R-Car
Gen2. SDHI1 IP on the other hand is compatible with R-Car
Gen3 with internal DMA.
This patch completes the SDHI support of the R-Car Gen2
compatible IPs, including fixing the max-frequency
definition of SDHI2, as it turns out there is a bug in
Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev.
1.00 Oct. 2017).

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:22 +01:00
Fabrizio Castro
4f94af5723 ARM: dts: r8a77470: Add I2C[0123] support 
Add device tree nodes for the I2C[0123] controllers. Also, add
the aliases node.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-11-28 13:55:21 +01:00
Fabrizio Castro
3578859661 ARM: dts: r8a77470: Add I2C4 support 
Add I2C4 support to RZ/G1C (a.k.a. r8a77470) SoC specific
device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-09-28 10:32:49 +02:00
Fabrizio Castro
f068cc8160 ARM: dts: r8a77470: Add SDHI2 support 
Add SoC specific device tree definitions for the SDHI2 interface.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-09-28 10:32:48 +02:00
Fabrizio Castro
a21efdbc74 ARM: dts: r8a77470: Add SMP support 
Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-09-28 10:32:47 +02:00
Biju Das
5fcd4bfe03 ARM: dts: r8a77470: Add GPIO support 
Describe GPIO blocks in the R8A77470 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-08-27 15:02:13 +02:00
Biju Das
0ea1a4d2c9 ARM: dts: r8a77470: Add PFC support 
Define the generic R8A77470 part of the PFC device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-08-27 15:02:12 +02:00
Biju Das
f892c0c70e ARM: dts: r8a77470: Use r8a77470-sysc binding definitions 
Replace the hardcoded power domain indices by R8A77470_PD_* symbols.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-08-27 15:02:12 +02:00
Geert Uytterhoeven
c03e2f12a2 ARM: dts: r8a77470: Use r8a77470-cpg-mssr binding definitions 
Replace the hardcoded clock indices by R8A77470_CLK_* symbols.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-07-23 13:33:06 +02:00
Biju Das
f70b0958c0 ARM: dts: r8a77470: Add EtherAVB support 
Define the generic R8A77470 part of the EtherAVB device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-04-30 09:52:19 +02:00
Biju Das
e469612220 ARM: dts: r8a77470: Add SCIF DMA support 
Add SCIF DMA support for R8A77470 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-04-25 08:51:21 +02:00
Biju Das
8cdb8f1ab7 ARM: dts: r8a77470: Add SCIF support 
Describe SCIF ports in the R8A77470 device tree.
Also it fixes the CPG clock index ZS from 6 to 5.

Fixes: 6929dfc591 ("ARM: dts: r8a77470: Initial SoC device tree")
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-04-25 08:51:20 +02:00
Biju Das
141fb10294 ARM: dts: r8a77470: Add IRQC support 
Describe the IRQC interrupt controller in the R8A77470 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-04-25 08:51:02 +02:00
Biju Das
2e5775e3fd ARM: dts: r8a77470: Add SYS-DMAC support 
Describe SYS-DMAC0/1 in the R8A77470 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-04-25 08:51:01 +02:00
Biju Das
6929dfc591 ARM: dts: r8a77470: Initial SoC device tree 
The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
 2018-04-16 16:01:55 +02:00