2 Commits

Author	SHA1	Message	Date
Jon Mason	f713c6bf32	clk: iproc: Split off dig_filter ... The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2015-10-21 17:02:57 -07:00
Jon Mason	5f024b0685	clk: nsp: add clock support for Broadcom Northstar Plus SoC ... The Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2015-10-21 16:53:20 -07:00