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749 Commits

Author SHA1 Message Date
Uwe Kleine-König
f00b45db02 clk: Switch back to struct platform_driver::remove() 
After commit 0edb555a65 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all clk drivers to use .remove(), with the eventual goal to drop
struct platform_driver::remove_new(). As .remove() and .remove_new() have
the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-09-21 14:12:05 -07:00
Stephen Boyd
c7183ff52f Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next 
* clk-assigned-rates:
  clk: clk-conf: support assigned-clock-rates-u64

* clk-renesas: (34 commits)
  clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
  clk: renesas: rzv2h: Add support for dynamic switching divider clocks
  clk: renesas: r9a08g045: Add clocks, resets and power domains for USB
  dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints
  clk: renesas: r8a779h0: Add CANFD clock
  clk: renesas: Add RZ/V2H(P) CPG driver
  clk: renesas: Add family-specific clock driver for RZ/V2H(P)
  dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
  clk: renesas: r8a779h0: Add PWM clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock
  clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
  clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
  clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
  clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
  clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
  clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
  clk: renesas: r8a779a0: Use defines for PLL control registers
  clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
  clk: renesas: rcar-gen4: Add support for fixed variable PLLs
  clk: renesas: rcar-gen4: Add support for variable fractional PLLs
  ...

* clk-scmi:
  clk: scmi: add is_prepared hook
 2024-09-21 14:10:53 -07:00
Lad Prabhakar
3aeccbe081 clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT 
Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface
(RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-09-02 10:15:38 +02:00
Lad Prabhakar
bc4d25fdfa clk: renesas: rzv2h: Add support for dynamic switching divider clocks 
Add support for dynamic switching divider clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828093822.162855-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-09-02 10:15:38 +02:00
Claudiu Beznea
f0fe60cae6 clk: renesas: r9a08g045: Add clocks, resets and power domains for USB 
Add clocks, resets and power domains for USB modules available on the
Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-09-02 10:15:31 +02:00
Cong Dang
120c2833b7 clk: renesas: r8a779h0: Add CANFD clock 
Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be
 2024-08-20 09:48:24 +02:00
Lad Prabhakar
36932cbc3e clk: renesas: Add RZ/V2H(P) CPG driver 
Add RZ/V2H(P) CPG driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-08-20 09:48:24 +02:00
Rob Herring (Arm)
66b065239a clk: Use of_property_present() 
Use of_property_present() to test for property presence rather than
of_(find|get)_property(). This is part of a larger effort to remove
callers of of_find_property() and similar functions.
of_(find|get)_property() leak the DT struct property and data pointers
which is a problem for dynamically allocated nodes which may be freed.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240731191312.1710417-4-robh@kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # clk-mstp.c
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-08-02 16:53:38 -07:00
Lad Prabhakar
dd22e56217 clk: renesas: Add family-specific clock driver for RZ/V2H(P) 
Add family-specific clock driver for RZ/V2H(P) SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-08-02 11:23:05 +02:00
Cong Dang
ab52dd821f clk: renesas: r8a779h0: Add PWM clock 
Add the module clock used by the PWM timers on the Renesas R-Car V4M
(R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
[wsa: rebased]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240725194906.14644-9-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-08-02 11:23:04 +02:00
Geert Uytterhoeven
93d46d465f clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs 
The default PLL2/3/4/6 multiplier and divider configurations are no
longer used after the conversion to fixed or variable fractional PLL
clock types.

Note that the default configurations are still documented in the
comments above the individual rcar_gen4_cpg_pll_config instances.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:19 +02:00
Geert Uytterhoeven
f7444f0fde clk: renesas: rcar-gen4: Remove unused fixed PLL clock types 
All users of the fixed default PLL2/3/4/6 clock types have been
converted to fixed or variable fractional PLL clock types.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/c0229eb3518444f61173c6fb83bdcedb058dd079.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:19 +02:00
Geert Uytterhoeven
ccdf745bd1 clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type 
The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
2cf316b4c5 clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs 
Currently, all PLLs are modelled as fixed divider clocks, based on the
state of the mode pins.  However, the boot loader stack may have changed
the actual PLL configuration from the default, leading to incorrect
clock frequencies.

Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4,
and PLL6 as variable fractional PLLs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/3beac7c44534ed153ce7cea5c31f4b0bb7b16ab0.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
e1924c6cd1 clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs 
Currently, all PLLs but PLL2 are modelled as fixed divider clocks, based
on the state of the mode pins.  However, the boot loader stack may have
changed the actual PLL configuration from the default, leading to
incorrect clock frequencies.

Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4,
and PLL6 as variable fractional PLLs.

Reformat nearby lines to retain a consistent layout.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/b98523ed08de7386944c5ae860eae107dc28be3e.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
e4915fc7de clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs 
Currently, all PLLs are modelled as fixed divider clocks, based on the
state of the mode pins.  However, the boot loader stack may have changed
the actual PLL configuration from the default, leading to incorrect
clock frequencies.

Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, and
PLL6 as variable fractional PLLs.  Note that the R-Car Gen4 clock driver
does not support variable 9.24 PLLs yet, so the driver will downgrade
them to fixed fractional PLLs, too.

Reformat nearby lines to retain a consistent layout.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8544571f507e00ed6fc61617d27c9e19de5e9d11.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
4c63e9a135 clk: renesas: r8a779a0: Use defines for PLL control registers 
Add symbolic definitions for the various PLL control registers.
Replace hardcoded register offsets by the new definitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8cac464c7dfb15ecd299b8ab4ba88a16135f8123.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
732a6108ef clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs 
The custom clock driver that models the PLL clocks on R-Car Gen4
supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M.
R-Car S4-8 uses integer and fractional multiplication fields that are
one bit larger resp. smaller, and a slightly different formula.

Extend the existing support to fractional 9.24 PLL, and introduce new
clock types and helper macros to describe these PLLs.

Note that there is no use case for variable fractional 9.24 PLLs yet, as
the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode.
Hence the PLL is always modeled as a fixed PLL, regardless of the
description,

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/5684eda1260435c8eceabc274e0b18cb280a6341.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
3284ffb74c clk: renesas: rcar-gen4: Add support for fixed variable PLLs 
The custom clock driver that models PLL clocks on R-Car Gen4 supports
variable clocks, while PLL1 uses a similar control register layout, but
is read-only.

Extend the existing support to fixed clocks and PLL1, and introduce a
new clock type and helper macro to describe a fixed PLL.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/841fbb63d472c357b3ce291a5991db3b847f96d8.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
724620bd71 clk: renesas: rcar-gen4: Add support for variable fractional PLLs 
The custom clock driver that models PLL clocks on R-Car Gen4 supports
PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same
control register layout.

Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new
clock type and helper macro to describe these PLLs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
1b131e08e7 clk: renesas: rcar-gen4: Add support for fractional multiplication 
R-Car Gen4 PLLs support fractional multiplication, which can improve
accuracy when configuring a specific frequency.

Add support for fractional multiplication to the custom clock driver
for PLLs, which is currently used only for PLL2 on R-Car V4H.
While at it, add the missing blank line after the function.

Note that Fractional Multiplication is not enabled by the driver,
but used only if the boot loaded enabled it before.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/1a58ebef6f54460f49fb81ba9bbf288164de2646.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
dd82ab4fdf clk: renesas: rcar-gen4: Use defines for common CPG registers 
Add symbolic definitions for common CPG registers.
Replace hardcoded register offsets by the new definitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8ae48a5dac59cb5723fbca3842b93a9e51ffe1ca.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
f719e59843 clk: renesas: rcar-gen4: Use FIELD_GET() 
Improve readability by using the FIELD_GET() helper instead of
open-coding the same operation, and by adding field definitions to get
rid of hardcoded values.

While at it, move register definitions that are only used inside the
rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file.
Add a "CPG_" prefix to SD0CKCR1.  Add comments where appropriate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/fb19ad829738f02effa340fa04c178a162d41202.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
9edc5c209d clk: renesas: rcar-gen4: Clarify custom PLL clock support 
The custom clock driver that models the PLL clocks on R-Car Gen4 assumes
the integer and fractional[*] multiplication field sizes as used on
R-Car V4H and V4M, representing a fractional 8.25 number.

Rename the related definitions, functions, and structures to clarify
this, and to prepare for the advent of support for the different field
sizes on R-Car S4-8.

[*] The fractional part is not yet supported.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/2ce9f9c75bfb6312129d416672f9691bbd11c0e7.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Geert Uytterhoeven
4897930deb clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions 
All SSMODE operations are done using CPG_PLLxCR0_SSMODE*.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/19f84bfec94eab5f301a9c33563c285ab59b9b2a.1721648548.git.geert+renesas@glider.be
 2024-07-30 10:44:18 +02:00
Lad Prabhakar
354e5cf4f6 clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock register functions 
Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and
`base` parameters in various clock registration functions. These values
are now accessed directly from the `priv` structure.

While at it, drop masking of parent clocks with 0xffff as nothing is ever
stored in the high bits.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240715103555.507767-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-07-30 10:44:18 +02:00
Lad Prabhakar
019b5ecc03 clk: renesas: rzg2l-cpg: Use devres API to register clocks 
We are using devres APIs for divider, mux and pll5 clocks so for
consistency use the devres APIs for module, fixed factor and PLL clocks.

While at it switched to clk_hw_register() instead of clk_register()
as this has been marked as deprecated interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240715103555.507767-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-07-30 10:44:17 +02:00
Geert Uytterhoeven
588d55aba0 clk: renesas: r8a779h0: Initial clock descriptions should be __initconst 
r8a779h0_core_clks[], r8a779h0_mod_clks[], and cpg_pll_configs[] are
only used during initialization.  Hence make them __initconst, so they
will be freed later.

Fixes: f077cab34d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/35bbcfb914ddb377fa77e3425e4e7e232c7c2cf9.1720794214.git.geert+renesas@glider.be
 2024-07-30 10:44:17 +02:00
Geert Uytterhoeven
898b5bc482 clk: renesas: r8a779g0: cpg_pll_configs should be __initconst 
cpg_pll_configs[] is only used during initialization.  Hence make it
__initconst, so it will be freed later.

Fixes: 0ab55cf183 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/ea806a096d47382f4f560b20f1038f03b4e44e0e.1720794214.git.geert+renesas@glider.be
 2024-07-30 10:44:17 +02:00
Geert Uytterhoeven
7d5c73d960 clk: renesas: r8a779f0: cpg_pll_configs should be __initconst 
cpg_pll_configs[] is only used during initialization.  Hence make it
__initconst, so it will be freed later.

Fixes: 24aaff6a6c ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/2261fc8291099445e1b319812dfd4f79c90296d2.1720794214.git.geert+renesas@glider.be
 2024-07-30 10:44:17 +02:00
Geert Uytterhoeven
bd721d922c clk: renesas: r8a779a0: cpg_pll_configs should be __initconst 
cpg_pll_configs[] is only used during initialization.  Hence make it
__initconst, so it will be freed later.

Fixes: 17bcc8035d ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/a9819625329b188c298481402e1c55ac46093518.1720794214.git.geert+renesas@glider.be
 2024-07-30 10:44:17 +02:00
Claudiu Beznea
6f5c16b74b clk: renesas: r9a08g045: Add DMA clocks and resets 
Add the missing DMA clock and resets.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240711123405.2966302-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-07-30 10:44:14 +02:00
Biju Das
10dfa837da clk: renesas: r9a07g043: Add LCDC clock and reset entries 
Add LCDC clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240709135152.185042-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-07-30 10:28:39 +02:00
Yoshihiro Shimoda
2331933314 clk: renesas: r8a779h0: Add PCIe clock 
Add the PCIe module clock, which is used by the PCIe module on the
Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240704061720.1444755-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-07-30 10:28:39 +02:00
Claudiu Beznea
c7e58843d1 clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C 
Add clock, reset and power domain support for the I2C channels available
on the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625121358.590547-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-27 18:17:13 +02:00
Kuninori Morimoto
1f5ed3ae02 clk: renesas: r8a779h0: Add Audio clocks 
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car
V4M (R8A779H0) SoC.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/87h6djkxf2.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-27 18:17:00 +02:00
Claudiu Beznea
c8bd9bd644 clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP 
The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB)
that generates the RTC clock. Add clock, reset and power domain support
for it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-27 18:16:39 +02:00
Geert Uytterhoeven
ebae969d2f clk: renesas: Drop "Renesas" from individual driver descriptions 
All configuration options are under the big "Renesas SoC clock support"
umbrella, so there is no reason to repeat this for each driver.
Hence drop "Renesas" from the few that do.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/185323de4d38b9b599775c1b64ce4171551b98d5.1718177124.git.geert+renesas@glider.be
 2024-06-24 15:51:06 +02:00
Geert Uytterhoeven
362951fef4 clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments 
The multipliers for PLL2 and PLL4 as listed in the comments for
the cpg_pll_configs[] array are incorrect.  Fix them.

Note that the actual values in the tables were correct.

Fixes: f077cab34d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
 2024-06-24 15:51:04 +02:00
Niklas Söderlund
f92d44a00b clk: renesas: r8a779h0: Add VIN clocks 
Add the VIN module clocks, which are used by the VIN modules on the
Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240606170858.1694652-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:36:27 +02:00
Geert Uytterhoeven
2092760681 clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock 
A static spinlock can be initialized automatically with
DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init().

Suggested-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/8da2c908f00043f05f7e26e3c26400aea0cfe8bc.1716975021.git.geert+renesas@glider.be
 2024-06-07 14:10:15 +02:00
Geert Uytterhoeven
3b2f834dd3 clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock 
A global spinlock can be initialized automatically with
DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init().

Suggested-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/9073a6bfb7791e492156331fa8a0ea87a7c7cef6.1716975021.git.geert+renesas@glider.be
 2024-06-07 14:09:59 +02:00
Geert Uytterhoeven
c001f9c9bc clk: renesas: r8a77970: Use common cpg_lock 
R-Car Gen3 Socs use the common CPG/MSSR library functions in
rcar-cpg-lib.c, so the R-Car V3M sub-driver can use the common cpg_lock
instead of a driver-private lock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/0cd9b5ffbe986bd7dc4ffb3f13492123432ee2e1.1716975021.git.geert+renesas@glider.be
 2024-06-07 14:09:34 +02:00
Niklas Söderlund
7c8730df59 clk: renesas: r8a779h0: Add CSI-2 clocks 
Add the CSI40 and CSI41 module clocks, which are used by the CSI-2
interfaces on the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240527131541.1676525-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-03 09:46:18 +02:00
Niklas Söderlund
babc0ea4e6 clk: renesas: r8a779h0: Add ISPCS clocks 
Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS
modules on the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240527131541.1676525-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-03 09:45:54 +02:00
Claudiu Beznea
5add5ebc4e clk: renesas: r9a08g045: Add support for power domains 
Instantiate power domains for the currently enabled IPs of the R9A08G045
SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-04-25 20:12:17 +02:00
Claudiu Beznea
0c8a59b311 clk: renesas: rzg2l: Extend power domain support 
RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
power when clocks are disabled by activating module standby.  This is
done through MSTOP-specific registers that are part of CPG.  Each
individual module has one or more bits associated with one MSTOP
register (see table "Registers for Module Standby Mode" from HW
manuals).  Hardware manual associates modules' clocks with one or more
MSTOP bits.  There are 3 mappings available (identified by researching
RZ/G2L, RZ/G3S, RZ/V2L HW manuals):

case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})

Case 3 has been currently identified on RZ/V2L for the VCPL4 module.

To cover all three cases, the individual platform drivers will provide
the clock driver with MSTOP register offsets and associated bits in this
register as a bitmask, and the clock driver will apply this bitmask to
the proper MSTOP register.

The MSTOP support was implemented through power domains.
Platform-specific clock drivers will register an array of type struct
rzg2l_cpg_pm_domain_init_data, which will be used to instantiate
properly the power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-7-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-04-25 20:12:15 +02:00
Geert Uytterhoeven
d0d4585222 clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT 
CLK_ENABLE_ON_INIT is a relic from the old SH clock framework.
It is not used on SH/R-Mobile ARM drivers.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f01e60a1007afe9385ddc10c4665752857ba4135.1714032122.git.geert+renesas@glider.be
 2024-04-25 10:38:19 +02:00
Christophe JAILLET
1b1f8cc204 clk: renesas: r8a7740: Remove unused div4_clk.flags field 
In "struct div4_clk", the "flags" field is unused.

Remove it, and update the "div4_clks" array accordingly.

Found with cppcheck, unusedStructMember.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/658e6b1b23d5b66646bb830361b8c55ccf797771.1713025170.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-04-25 10:37:00 +02:00
Lad Prabhakar
44019387fc clk: renesas: r9a07g043: Add clock and reset entry for PLIC 
Add the missing clock and reset entry for PLIC. Also add
R9A07G043_NCEPLIC_ACLK to the critical clocks list.

Fixes: 95d48d2703 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-04-23 09:36:49 +02:00