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19 Commits

Author SHA1 Message Date
Qili Lu
f5a972dfe3 drm/amd/display: fix dccg root clock optimization related hang 
[Why]
enable dpp rcg before we disable dppclk in hw_init cause system
hang/reboot

[How]
we remove dccg rcg related code from init into a separate function and
call it after we init pipe

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Qili Lu <qili.lu@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-09-06 17:41:07 -04:00
Nicholas Susanto
5359d5bc97 drm/amd/display: Refactor dccg35_get_other_enabled_symclk_fe 
[Why]

Function used to check the number of FEs connected to the current BE.
This was then used to determine if the symclk could be disabled, if
all FEs were disconnected. However, the function would skip over the
primary FE and return 0 when the primary FE was still connected. This
caused black screens on driver disable with an MST daisy chain hooked
up.

[How]

Refactor the function to correctly return the number of FEs connected
to the input BE. Also, rename it for clarity.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Nicholas Susanto <Nicholas.Susanto@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-09-06 17:40:55 -04:00
Hansen Dsouza
9888773753 drm/amd/display: Fix flickering caused by dccg 
Always allow un-gating. Follow legacy workaround for repeated
dppclk dto updates

Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-09-02 11:39:53 -04:00
Ahmed, Muhammad
5d666496c2 drm/amd/display: guard write a 0 post_divider value to HW 
[why]
post_divider_value should not be 0.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Ahmed, Muhammad <Ahmed.Ahmed@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-27 17:51:53 -04:00
Hansen Dsouza
18ac82c26d Revert "drm/amd/display: Update to using new dccg callbacks" 
[Why]
Revert updated DCCG wrappers due to regression

[How]
This reverts commit 680458d41a.

Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-20 22:14:13 -04:00
Hansen Dsouza
680458d41a drm/amd/display: Update to using new dccg callbacks 
[Why and how]
Update to using new dccg callbacks

Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-13 10:32:29 -04:00
Hansen Dsouza
00f06855f6 drm/amd/display: Add clock control callbacks 
[why & how]
Add clock source selection control functions based on spec

Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-06 11:11:03 -04:00
Hansen Dsouza
78c508a1c1 drm/amd/display: Add clock control callbacks 
[why & how]
Add clock source selection an control functions based on spec

Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-06 11:11:02 -04:00
Hansen Dsouza
64a905203f drm/amd/display: Add stream and char control callback 
[why & how]
Add new stream and char control functions based on DCCG spec

Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-08-06 11:11:01 -04:00
Hansen Dsouza
c9bfc37f08 drm/amd/display: Add new enable and disable functions for DCN35 
Add new enable and disable functions based on DCCG spec.

Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-07-27 17:35:55 -04:00
Hansen Dsouza
b5126ba85b drm/amd/display: Add new enable and disable functions 
Add new enable and disable functions based on DCCG spec.

Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-07-27 17:35:15 -04:00
Hansen Dsouza
f52ea01925 drm/amd/display: Add source select helper functions 
[why & how]
Add source select helpers based on DCCG spec

Reviewed-by: Daniel Miess <daniel.miess@amd.com>
Signed-off-by: Hansen Dsouza <hansen.dsouza@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-07-23 17:36:21 -04:00
Hansen Dsouza
14d6ca0740 drm/amd/display: Add RCG helper functions 
[why & how]
Add standard RCG helpers based on DCCG spec

Reviewed-by: Daniel Miess <daniel.miess@amd.com>
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Hansen Dsouza <hansen.dsouza@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-07-23 17:35:57 -04:00
Hansen Dsouza
3f7477bfbb drm/amd/display: Add private data type for RCG 
[why & how]
Add private data types for better RCG control

Reviewed-by: Chris Park <chris.park@amd.com>
Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Signed-off-by: Hansen Dsouza <hansen.dsouza@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-07-23 17:35:39 -04:00
yi-lchen
975507d73c drm/amd/display: Keep VBios pixel rate div setting until next mode set 
[why]
Vbios & Driver have difference pixel rate div policy.
When enabling fast boot & performing blank & unblank w/o timing setting,
pixel clock & pixel rate dividor are not match.
It would cause too high pixel reate and eDP would be black screen.

[How]
We would keep pixel rate div setting by Vbios until next timing setting.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: yi-lchen <yi-lchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-05 11:04:50 -04:00
Alex Hung
56116dc7a9 Revert "drm/amd/display: Enable SYMCLK gating in DCCG" 
This reverts commit c49e44ede5.

This causes regression on DP link layer test.

Reported-by: Mark Broadworth <Mark.Broadworth@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-13 15:48:45 -04:00
Daniel Miess
c49e44ede5 drm/amd/display: Enable SYMCLK gating in DCCG 
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-13 15:47:08 -04:00
Alex Hung
3941a3aa4b drm/amd/display: Fix incorrect size calculation for loop 
[WHY]
fe_clk_en has size of 5 but sizeof(fe_clk_en) has byte size 20 which is
lager than the array size.

[HOW]
Divide byte size 20 by its element size.

This fixes 2 OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:16 -04:00
Revalla Hari Krishna
0a8d25285f drm/amd/display: Refactor DCCG into component folder 
[why]
cleaning up the code refactor requires dccg to be in its own component.

[how]
move all files under newly created dccg folder and fixing the
makefiles.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Revalla Hari Krishna <harikrishna.revalla@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:16 -04:00