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83 Commits

Author SHA1 Message Date
Tejas Upadhyay
da9a73b7b2 drm/xe/xe2hpg: Add Wa_15016589081 
Wa_15016589081 applies to xe2_hpg renderCS

V2(Gustavo)
  - rename bit macro

Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240904101333.2049655-1-tejas.upadhyay@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
(cherry picked from commit 9db969b36b)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-09-12 18:04:36 -05:00
Tejas Upadhyay
21ff3a16e9 drm/xe/xe2hpg: Add Wa_14021821874 
Wa_14021821874 applies to xe2_hpg

V2(Himal):
  - Use space after define

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240812134117.813670-1-tejas.upadhyay@intel.com
 2024-08-12 16:47:55 -07:00
Lucas De Marchi
66ac3451fb drm/xe: Add assert for XE_WA() usage 
It's not always safe to call XE_WA() in the driver initialization. Add a
xe_gt_assert() so this doesn't go unnoticed.

While at it, fix typo in kernel-doc about OOB workarounds.

Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240722160815.4085605-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-07-24 09:05:37 -07:00
Bommu Krishnaiah
56ab698699 drm/xe/xe2lpg: Extend workaround 14021402888 
workaround 14021402888 also applies to Xe2_LPG.
Replicate the existing entry to one specific for Xe2_LPG.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240703090754.1323647-1-krishnaiah.bommu@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-07-09 07:14:06 -07:00
Ngai-Mint Kwan
74e3076800 drm/xe/xe2lpm: Extend Wa_16021639441 
Wa_16021639441 applies to Xe2_LPM.

Signed-off-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240701184637.531794-1-ngai-mint.kwan@linux.intel.com
 2024-07-08 08:25:16 -07:00
Michal Wajdeczko
f20535ce1d drm/xe/vf: Don't apply tile workarounds if VF 
The VF drivers can't apply any workarounds as they don't have
access to related registers. Since xe_wa_apply_tile_workarounds()
function is not using RTP yet, we have to add early return.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619214557.905-4-michal.wajdeczko@intel.com
 2024-06-20 19:49:36 +02:00
Sai Teja Pottumuttu
d35386b3a7 drm/xe/xelpgp: Extend Wa_14019877138 to graphics 12.74 
Wa_14019877138 is also needed for xe_lpgp graphics 12.74

Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619065614.131151-1-sai.teja.pottumuttu@intel.com
 2024-06-20 09:45:00 -07:00
Lucas De Marchi
62712be3a4 drm/xe/xe2: Add proper check for media in Wa_14020756599 
A temporary fixup was made in commit 24d0d98af1 ("drm/xe/xe2lpm: Fixup
Wa_14020756599") due to limitations in the RTP infra. Now that RTP has
support for OR condition that change can be removed. RTP now also
supports checking any GT, so use that instead of the more specific
xe_rtp_match_when_media2000() used in that commit.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618050044.324454-6-lucas.demarchi@intel.com
 2024-06-18 12:03:30 -07:00
Akshata Jahagirdar
5d7612ae20 drm/xe/xe2lpg: Add Wa_14021490052 
Add Wa_14021490052 for Xe2LPG 20.04.

Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240614182455.2370059-2-matthew.d.roper@intel.com
 2024-06-15 21:13:28 -07:00
Tejas Upadhyay
24d0d98af1 drm/xe/xe2lpm: Fixup Wa_14020756599 
This WA needs to be applied to graphics GT when the media version
is 2000. Currently, media version 2000 is always paired with
graphics version 2004 which will result in writing same register
with same bits twice. We can't add optional rule in rtp
framework and also writing same register with same bits gives
warning.

Currently, media version 2000 is always paired with graphics version
2004, so just checking the latter is sufficient.

V2(Lucas):
  - Add more detail in commit message
  - Improve code comment to follow guideline

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2016
Fixes: 131328aa56 ("drm/xe/xe2lpm: Add permanent Wa_14020756599")
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607122528.1048610-1-tejas.upadhyay@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-06-11 08:21:01 -07:00
Tejas Upadhyay
c393538e01 drm/xe/xe2lpg: Add permanent wa_14020756599 
For xe2_lpg render Wa_14020756599 is applied to
all steppings.

Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240603104951.705603-3-tejas.upadhyay@intel.com
 2024-06-04 23:21:27 -07:00
Tejas Upadhyay
131328aa56 drm/xe/xe2lpm: Add permanent Wa_14020756599 
For xe2_lpm Wa_14020756599 is applied to all steppings and
when RCS is present on graphics GT.

V5(MattR):
  - Add more comments about new API
V4:
  - Make it part of lrc wa
  - Check for RCS as rtp rule
V3(MattR):
  - Rename rtp api name
  - Use MEDIA_VERx100
V2:
  - Remove engine filter video decode
  - Fix typo GRAPHICS/MEDIA/s - Himal

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240603104951.705603-2-tejas.upadhyay@intel.com
 2024-06-04 23:21:26 -07:00
Riana Tauro
9276bcc22f drm/xe: Standardize power gate registers 
Standardize power gate registers

No functional changes

v2: change commit message (Rodrigo)

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-2-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2024-05-28 12:29:42 -04:00
Bommu Krishnaiah
598dc939ed drm/xe/xe2: Add workaround 14021402888 
This workaround applies to Graphics 20.01 as RCS engine workaround

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240418111534.481568-1-krishnaiah.bommu@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-05-08 14:24:50 -07:00
Lucas De Marchi
4caf410766 drm/xe: Merge 16021540221 and 18034896535 WAs 
In order to detect duplicate implementations for the same workaround,
early in the implementation of RTP it was decided to error out even if
the values set are exactly the same. With the introduction of 18034896535
in commit 74671d23ca ("drm/xe/xe2: Add workaround 18034896535"), LNL
stepping with graphics stepping A1 now gives the following error on
module load:

	xe 0000:00:02.0: [drm] *ERROR* GT0: [GT OTHER] \
	discarding save-restore reg e48c (clear: 00000200, set: 00000200,\
	masked: yes, mcr: yes): ret=-22

RTP may be improved in the future, but for now simply join the entries
like done with e.g. "1607297627, 1607030317, 1607186500".

Fixes: 74671d23ca ("drm/xe/xe2: Add workaround 18034896535")
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240427135339.3485559-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-04-29 08:03:23 -07:00
Shekhar Chauhan
bb442bfb9b drm/xe/xe2hpg: Add Wa_14021490052 
Add Wa_14021490052 for Xe2HPG 20.01.

Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240424034247.1352755-1-shekhar.chauhan@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-04-29 07:04:39 -07:00
Tejas Upadhyay
b5ef80879d drm/xe/xe2: Add workaround 14021567978 
Workaround 14021567978 applies to RenderCS xe2

V3:
  - Cover xe2_hpg as its landed upstream now
V2(MattR):
  - Move tuning to wa and apply to xe2

Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240410064640.1010098-1-tejas.upadhyay@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-04-24 15:34:01 -07:00
Gustavo Sousa
cba22c911c drm/xe/xe2lpg: Extend Wa_14020338487 
Wa_14020338487 also applies to Xe2_LPG. Replicate the existing entry to
one specific for Xe2_LPG.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417212501.312346-1-gustavo.sousa@intel.com
 2024-04-18 11:01:56 -07:00
Gustavo Sousa
7cd05ef89c drm/xe/xe2hpm: Add initial set of workarounds 
Define the initial set of workarounds for Xe2_HPM.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-12-balasubramani.vivekanandan@intel.com
 2024-04-09 14:22:04 -07:00
Haridhar Kalvala
7f3ee7d880 drm/xe/xe2hpg: Add initial GT workarounds 
Add the initial set of Xe2_HPG gt/engine/lrc workarounds.

v2: Removed WA_16020183090 which is no more applicable
    Extended WA_18033852989,18034896535 also to xe2hpg

Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Dnyaneshar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-10-balasubramani.vivekanandan@intel.com
 2024-04-09 14:22:04 -07:00
Bommu Krishnaiah
74671d23ca drm/xe/xe2: Add workaround 18034896535 
Add 18034896535 as driver permanent workaround.

v2: 18034896535 and 16021540221 are two independent workarounds
that just happen to have the same implementation, hence keeping it.

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-9-balasubramani.vivekanandan@intel.com
 2024-04-09 14:22:04 -07:00
Himal Prasad Ghimiray
9f18b55b6d drm/xe/xe2: Add workaround 18033852989 
This workaround applies to RCS engine's context, hence added as
LRC workaround.

v2
- Fix commit description as lrc workaround instead of engine.(Lucas)

v3
- COMMON_SLICE_CHICKEN1 is a masked register, add XE_REG_OPTION_MASKED
flag. (Matt)

BSPEC: 55899

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240401163806.3821128-1-himal.prasad.ghimiray@intel.com
 2024-04-02 12:11:41 -07:00
Radhakrishna Sripada
0267ee1914 drm/xe/xelpg: Add Wa_14020495402 
Disable clockgating for TDL SVHS fub.

v2: Extend the Wa to 1274(MattR)

Bspec: 46045
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240318210120.564692-1-radhakrishna.sripada@intel.com
 2024-03-20 12:29:17 -07:00
Lucas De Marchi
71e721485c drm/xe/pvc: Fix WA 18020744125 
With the current state GUC_WA_RCS_REGS_IN_CCS_REGS_LIST could in theory
be removed since there is no render register being added to the list of
compute WAs. However the real issue is that 18020744125 is incomplete
and not setting the RING_HWSTAM on render as it should.

Writing this in RTP is a little more tricky as we want to write to
another's engine base when the match happens: first compute engine and
no render present. So use RING_HWSTAM(RENDER_RING_BASE) instead of the
usual XE_RTP_ACTION_FLAG(ENGINE_BASE).

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240306192128.1895603-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-03-08 10:19:26 -08:00
Lucas De Marchi
e89f4967d9 drm/xe: Drop WA 16015675438 
With dynamic load-balancing disabled on the compute side, there's no
reason left to enable WA 16015675438. Drop it from both PVC and DG2.

Note that this can be done because now the driver always set a fixed
partition of EUs during initialization via the ccs_mode configuration.

Cc: Mateusz Jablonski <mateusz.jablonski@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Acked-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240304233103.1687412-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-03-06 05:27:08 -08:00
Matt Roper
70e8602984 drm/xe/xelpg: Extend some workarounds to graphics version 12.74 
A handful of Xe_LPG workarounds are also relevant to graphics version
12.74 as well. Extend the graphics version range for these workarounds
accordingly.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240229070806.3402641-3-dnyaneshwar.bhadane@intel.com
 2024-03-05 16:38:56 -08:00
Dafna Hirschfeld
a24d909977 drm/xe: Do not include current dir for generated/xe_wa_oob.h 
The generated file 'generated/xe_wa_oob.h' is included using:
"generated/xe_wa_oob.h"
which first look inside the source code. But the file resides
in the build directory and should therefore be included using:
<generated/xe_wa_oob.h>

Signed-off-by: Dafna Hirschfeld <dhirschfeld@habana.ai>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240221083622.1584492-1-dhirschfeld@habana.ai
 2024-02-21 21:53:15 -08:00
Shekhar Chauhan
9fbedddfc9 drm/xe/xe2_lpg: Add Wa_16018610683 
Force max 128KB SLM during WMTP PASS1 Restore.

BSpec: 70202
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20240109055550.679289-1-shekhar.chauhan@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
 2024-01-09 10:39:43 -08:00
Lucas De Marchi
570a8fc233 drm/xe/xe2: Add workaround 16020183090 
Graphics version 20.04, used in Lunar Lake, needs WA 16020183090 for
steppings A*. Set ENABLE_SEMAPHORE_POLL_BIT in INSTPM(RENDER_RING_BASE)
and whitelist CSBE_DEBUG_STATUS for userspace to be able to use it
and complement the workaround.

Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231207175117.2334022-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2023-12-26 22:22:04 -08:00
Tejas Upadhyay
c5be725eb0 drm/xe/xelpg: Extend Wa_14019877138 for Graphics 12.70/71 
Wa_14019877138 is also needed for xe_lpg graphics 12.70/71

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
 2023-12-21 16:31:30 -05:00
Matt Roper
4e124151fc drm/xe/dg2: Drop pre-production workarounds 
Pre-production hardware is anything before C0 (for DG2-G10), before B1
(for DG2-G11), or before A1 (for DG2-G12).  Workarounds specific to such
hardware was already removed from i915 in commit eaeb4b3614
("drm/i915/dg2: Drop pre-production GT workarounds") and there's even
less value keeping these around in the Xe driver.

v2:
 - Drop Wa_14011441408 from xe_mocs.c.  (Gustavo)
 - Drop Wa_14010648519, Wa_14010198302, and Wa_1608949956 which were
   mis-implemented; they were only supposed to apply to early steppings
   of DG2-G10, but were being applied unconditionally on all DG2.
   (Gustavo)
 - Drop reference to Wa_16011620976; the implementation stays because it
   still matches Wa_22015475538.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231215214531.2576215-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
 2023-12-21 16:31:29 -05:00
Matt Roper
5ea7fe65fb drm/xe: Move some per-engine register definitions to the engine header 
Although we only work with the RCS instances today, the
FF_SLICE_CS_CHICKEN1[1,2] CS_DEBUG_MODE1, CS_CHICKEN1, and
FF_THREAD_MODE registers all have instances on both the RCS and CCS
engines.  Convert these to parameterized macros and move them to the
engine register header.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-12-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:46:16 -05:00
Matt Roper
bc17ec0b20 drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1 
We don't use this suffix on any other registers, and it isn't part of
the register's official name either, so drop it for consistency.

While at it, move the register definition slightly so that it isn't
separating RING_CMD_CCTL's definition from its fields.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-11-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:46:16 -05:00
Tejas Upadhyay
b279b53015 drm/xe/xe2: Add workaround 18032095049 and 16021639441 
This workaround applies to graphics 20.04 on all engines.

Workaround has three parts :
1. Pipe flush before MI_ATOMIC - This part isn't relevant to Xe
   (at least not right now) since we don't use MI_ATOMIC anywhere
   in the kernel mode driver.
2. Memory-based interrupt masking - Memory-based interrupt processing
   isn't supported on physical functions, only virtual functions,
   according to bspec 60352. So this is probably only relevant once
   SRIOV support lands in the driver.
3. Disabling CSB/timestamp updates to the ghwsp and pphwsp - Workaround
   is added by this change.

The CSB reports to gHWSP and ppHWSP have been discussed as part
of a different topic on some internal threads and we've confirmed
that neither the KMD nor the GuC firmware use those for anything,
so disabling them is always "safe" and should have no functional
or performance impact on system operation.  The same is true for
the timestamp updates in the ppHWSP as well.  Given that, it might
make sense to just combine these two workarounds into a single
record (and single patch) and apply it on all steppings. Disabling
the reports for RCS on higher steppings doesn't have any kind of
negative impact and will simplify the overall situation.

V3(MattR):
  - Combine WA apply same WA for all engines, no performance impact
V2(MattR):
  - Mention detail in commit message
  - Reorder bit define
  - Improve bit naming
  - Remove workaround part which isnt relevant

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:45:24 -05:00
Tejas Upadhyay
6a1fd6787d drm/xe/xe2: Add workaround 14019988906 
This workaround applies to Graphics 20.04 as engine
workaround

V2(MattR):
 - Reorder bit define
 - Apply WA for RCS only

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:45:24 -05:00
Tejas Upadhyay
a409901f51 drm/xe/xe2: Add workaround 14020013138 
This workaround applies to Xe2_LPG A0

V3:
  - Apply rule RENDER class
V2(Matt):
  - Apply WA in lrc context

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:45:05 -05:00
Matt Roper
f91bacce8d drm/xe/dg2: Drop Wa_22014600077 
The workaround database has been updated to drop this workaround for all
DG2 variants.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231127190332.4099519-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:45:05 -05:00
Tejas Upadhyay
8bfbe174d7 drm/xe/xe2: Add workaround 14019449301 
This workaround applies to Xe2_LPM

V3(MattR):
  - Reorder reg and wa placement
  - Add base parameter to reg macro for better definition
V2(MattR):
  - Change name of register
  - Loop for all engines
  - Driver permanent WA, applies to all steps

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:44:56 -05:00
Tejas Upadhyay
f25d8291ac drm/xe/xe2: Add workaround 16021867713 
This workaround applies to Xe2_LPM as well

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:44:56 -05:00
Tejas Upadhyay
11ea758c14 drm/xe/xe2: Add workaround 14017421178 
This workaround applies to Xe2_LPM

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:44:56 -05:00
Matt Roper
32dd40fb48 drm/xe/dg2: Wa_18028616096 now applies to all DG2 
The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231115183029.2649992-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:44:38 -05:00
Haridhar Kalvala
047d1f6a2f drm/xe: Add Wa_14019877138 
Enable Force Dispatch Ends Collection for DG2.

BSpec: 46001
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231108073351.3998413-1-haridhar.kalvala@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:43:38 -05:00
Gustavo Sousa
6ffef7b699 drm/xe/xelpmp: Add Wa_16021867713 
This workaround applies to all steppings of Xe_LPM+. Implement the KMD
part.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231106210655.175109-3-gustavo.sousa@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:43:34 -05:00
Shekhar Chauhan
7eea3fb67a drm/xe/xelpmp: Extend Wa_22016670082 to Xe_LPM+ 
Add Xe_LPM+ support to an existing workaround.

BSpec: 51762
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://lore.kernel.org/r/20231030150756.1011777-1-shekhar.chauhan@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:43:31 -05:00
Lucas De Marchi
65e9573588 drm/xe: Fix WA 14010918519 write to wrong register 
FORCE_SLM_FENCE_SCOPE_TO_TILE and FORCE_UGM_FENCE_SCOPE_TO_TILE are in
the up dword of LSC_CHICKEN_BIT_0 register. Also, the 14010918519
workaround only applies to early steppings, A*. Eventually those should
be dropped, like they were in commit eaeb4b3614 ("drm/i915/dg2: Drop
pre-production GT workarounds"), so let's make sure they are annotated
appropriately.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231024220412.223868-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:43:26 -05:00
Dnyaneshwar Bhadane
bad3644dd8 drm/xe/xe2: Add initial workarounds 
Add the initial collection of gt/engine/lrc workarounds.
While at it, add some newlines around the platform/IP comments to make
them consistent across all workarounds.

v2:
  - FF_MODE is an MCR register (Matt Roper)
  - Group 18032247524 with other Xe2 workarounds (Matt Roper)
  - Move WA changing PSS_CHICKEN to lrc_was[] as for Xe2 that register
    is part of the render context image (Matt Roper)
  - Apply WA 16020518922 only on render engine (Matt Roper)

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231024220739.224251-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:43:19 -05:00
Shekhar Chauhan
5fdd4b21ae drm/xe: Add Wa_18028616096 
Drop UGM per set fragment threshold to 3

BSpec: 54833
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230925160543.915217-1-shekhar.chauhan@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:41:16 -05:00
Matt Roper
0d0534750f drm/xe/wa: Apply tile workarounds at probe/resume 
Although the vast majority of workarounds the driver needs to implement
are either GT-based or display-based, there are occasionally workarounds
that reside outside those parts of the hardware (i.e., in they target
registers in the sgunit/soc); we can consider these to be "tile"
workarounds since there will be instance of these registers per tile.
The registers in question should only lose their values during a
function-level reset, so they only need to be applied during probe and
resume; the registers will not be affected by GT/engine resets.

Tile workarounds are rare (there's only one, 22010954014, that's
relevant to Xe at the moment) so it's probably not worth updating the
xe_rtp design to handle tile-level workarounds yet, although we may want
to consider that in the future if/when more of these show up on future
platforms.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20230913231411.291933-13-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:41:14 -05:00
Niranjana Vishwanathapura
7407f2e5c3 drm/xe/pvc: Force even num engines to use 64B 
Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.

v2: Move WA from engine_was[] to lrc_was[]

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:40:27 -05:00
Shekhar Chauhan
0955d3be8b drm/xe/dg2: Remove Wa_15010599737 
Since this is specific to DirectX, we don't need it on Linux.

Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230814150323.874033-1-shekhar.chauhan@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 2023-12-21 11:40:20 -05:00