As specified by the datasheet we should write the value 0x3 (enable
plus tracking gain) into the MU_CNT1 register during the MU lock phase.
Currently we were only setting the enable bit (bit 0) as the tracking
gain default value is already set to 1. While we should be mostly fine
in assuming the tracking gain will have the value it should, better to
explicitly write it. On top of that the datasheet also states to
re-attempt the writes in case the lock fails which we were not doing for
the tracking gain bit.
Lastly, the recommended value for the MU phase slope lock (bit 6) is 0
but for some reason the default value is 1 and hence, we were not
changing it accordingly.
Note there was no problem with the MU lock mechanism so this is not
being treated as a fix but rather an improvement.
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240429-ad9739a-improv-v1-1-c076a06a697d@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are capable
of synthesizing wideband signals from DC up to 3 GHz.
A dual-port, source synchronous, LVDS interface simplifies the digital
interface with existing FGPA/ASIC technology. On-chip controllers are used
to manage external and internal clock domain variations over temperature to
ensure reliable data transfer from the host to the DAC core.
Co-developed-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-10-5ca45b4de294@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
