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2 Commits

Author SHA1 Message Date
Yongqiang Sun
880af2eaed drm/amd/display: cap dpp dto phase not more than modulo. 
[Why]
4K monitor shows corruption if dpp dto phase is larger than modulo.

[How]
cap phase value never larger than modulo.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-11-10 14:26:18 -05:00
Yongqiang Sun
c07cbc1f04 drm/amd/display: update dpp dto phase and modulo. 
[Why & How]
Program modulo with ref dpp clk Mhz/10.
Program phase with pipe dpp clk Mhz /10.
DMUB FW could use these value to determine optimization clk
for PSR power saving.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-11-10 14:25:38 -05:00