usb0 was disabled by mistake when merging, so enable it.
Fixes: e7c304c034 ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
The Starfive VisionFive 2 has a 16MiB NOR flash, while the reserved-data
partition is declared starting at address 0x600000 with a size of
0x1000000. This causes the kernel to output the following warning:
[ 22.156589] mtd: partition "reserved-data" extends beyond the end of device "13010000.spi.0" -- size truncated to 0xa00000
It seems to be a confusion between the size of the partition and the end
address. Fix that by specifying the right size.
Fixes: 8384087a42 ("riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add temperature sensor and thermal-zones support for
the StarFive JH7110 SoC. CPUFreq cooling is supported
in thermal-zones.
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
v1.3B:
v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
inverse configurations.
The tx_clk of v1.3B uses an external clock and needs to be
switched to an external clock source.
v1.2A:
v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
configurations.
v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
switch rx and rx to external clock sources.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
[conor: squashed a fix from Samin to use the actual properties]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add the '-@' DTC option for the starfive devices. This option
populates the '__symbols__' node that contains all the necessary symbols
for supporting device-tree overlays (for instance from the firmware or
the bootloader) on these devices.
The starfive devices allow various modules to be connected and this
enables users to create out-of-tree device-tree overlays for these modules.
Please note that this change does increase the size of the resulting DTB
by ~20%. For example, with v6.4 increase in size is as follows:
jh7100-beaglev-starlight.dtb 6192 -> 7339
jh7100-starfive-visionfive-v1.dtb 6281 -> 7428
jh7110-starfive-visionfive-2-v1.2a.dtb 11101 -> 13447
jh7110-starfive-visionfive-2-v1.3b.dtb 11101 -> 13447
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO
variants. The canaan DTs are an outlier in that they're gated at the
directory and the file level. Drop the directory level gating while we
are swapping the symbol names over.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
In preparation for adding initial device tree support for the StarFive
VisionFive board, which is similar with BeagleV Starlight, move most
of the content from jh7100-beaglev-starlight.dts to a new file, to be
shared between the two boards.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
The PLIC integrated on the Vic_U7_Core integrated on the StarFive
JH7100 SoC actually supports 133 external interrupts. 127 of these
are exposed to the outside world; the remainder are used by other
devices that are part of the core-complex such as the L2 cache
controller. But all 133 interrupts are external interrupts as far
as the PLIC is concerned. Fix the property so that the driver can
manage these additional interrupts, which is important since the
interrupts for the L2 cache controller are enabled by default.
Fixes: ec85362fb1 ("RISC-V: Add initial StarFive JH7100 device tree")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220707185529.19509-1-kettenis@openbsd.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Add initial device tree for the BeagleV Starlight Beta board. About 300
of these boards were sent out as part of a now cancelled BeagleBoard.org
project.
I2C timing data is based on the device tree in the vendor u-boot port.
Heartbeat LED added by Geert.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.
The CPU and cache data is based on the device tree in the vendor u-boot
port.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
