Commit Graph

12937 Commits

Author SHA1 Message Date
Le.Ma
2beae55e39 drm/amdgpu: add structures for buffer allocate/release for rlc autoload
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC.

Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:36:07 -05:00
Hawking Zhang
edc611475a drm/amdgpu: add navi10 ih ip block (v3)
IH is the interrupt handler block.

v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squash in additional updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:30 -05:00
Hawking Zhang
f9df67e924 drm/amdgpu: add gmc v10 ip block for navi10 (v6)
GMC in the GPU memory controller.

v1: add place holder and initial basic implementation (Ray)
v2: retire unused amdgpu_gart_set_defaults (Hawking)
v3: re-work get_vm_pde function (Hawking)
v4: replace legacy amdgpu_vram/gtt_location with
    amdgpu_gmc_vram/gtt_location (Hawking)
v5: squash in updates (Alex)
v6: use get_vbios_fb_size (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Hawking Zhang
adc43c1b5e drm/amdgpu: add mmhub v2 block for navi10 (v4)
mmhub is the memory controller hub for multi-media (VCN).

v1: add place holder and initial functions (Ray)
v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Hawking Zhang
770b93e9ee drm/amdgpu: add gfxhub v2.0 block for navi10 (v4)
gfxhub is the memory controller hub for gfx and sdma.

v1: add place holder and initial basic functions (Ray)
v2: replace the refernce to legacy mc structure with gmc structure
    remove the direct use of gart.table_addr (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Jack Xiao
7f95167ce1 drm/amdgpu: refine the PTE encoding of PRT for navi10
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Hawking Zhang
7596ab68ff drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10
To differentiate the mtypes across asics.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Hawking Zhang
c304b9e519 drm/amdgpu: correct pte mtype field for navi
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Jack Xiao
367adb2ad5 drm/amdgpu/athub2: enable athub2 clock gating
Enable athub2 clock gating and light sleep

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:35:29 -05:00
Hawking Zhang
54fc447279 drm/amdgpu: create mqd for gfx queues on navi10
mqd is the memory queue descriptor for gfx and compute.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:24:54 -05:00
Jack Xiao
5bfca06928 drm/amdgpu: enable async gfx ring by default
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet.
Hence, enable async gfx ring by default.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:24:54 -05:00
Hawking Zhang
51bcce4621 drm/amdgpu: add module parameter for async_gfx_ring enablement
0 means disable async_gfx_ring and is the default setting
1 means enable async_gfx_ring

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:24:54 -05:00
Hawking Zhang
53b2fe415f drm/amdgpu: enable gfx eop interrupt per gfx pipe
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:24:54 -05:00
Jack Xiao
1919196165 drm/amdgpu/gfx10: add special unmap_queues packet for preemption
CP introduced a special unmap_queues packet for gfx preemtion.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:24:54 -05:00
Hawking Zhang
849aca9f9c drm/amdgpu: Move common code to amdgpu_gfx.c
move common code to amdgpu_gfx_enable_kcq,so
this function can be shared with gfx8 and gfx9

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:24:54 -05:00
Rex Zhu
ba0c13b774 drm/amdgpu: Add common gfx func Disable kcq via kiq
so can be shared with gfx8 and gfx9

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:21:06 -05:00
Rex Zhu
bc4a6f7135 drm/amdgpu: Add struct kiq_pm4_funcs into kiq struct
kiq can support 4 pm4 scheduler packets
set_resource, map_queues, unmap_queues, query_status.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:20:57 -05:00
Hawking Zhang
4fc6a88f01 drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_init
The function now will create mqd bos for both gfx queue and compute queue

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:20:51 -05:00
Hawking Zhang
7470bfcf20 drm/amdgpu: add helper function for gfx queue/bitmap transition
Similar to what we do for compute already.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:20:27 -05:00
Hawking Zhang
e537c99461 drm/amdgpu: acquire available gfx queues
currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:20:17 -05:00
Hawking Zhang
cf02b03f7c drm/amdgpu: add members in amdgpu_me for gfx queue
Update the structure for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:20:02 -05:00
Hawking Zhang
8825af65ff drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4)
gfx10 allows to only upload me jumptable while save the whole
me image at gtt memory.

v2: program CP_ME_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create me fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:19:56 -05:00
Hawking Zhang
2a00bb1322 drm/amdgpu/gfx10: new approach to load ce fw (v4)
gfx10 allows to only upload ce jumptable while save the whole
ce image at gtt memory.

v2: program CP_CE_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create ce fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:19:52 -05:00
Hawking Zhang
068ed934ee drm/amdgpu/gfx10: new approach to load pfp fw (v4)
gfx10 allows to only upload pfp jumptable while save the whole
pfp image at gtt memory.

v2: program CP_PFP_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:19:44 -05:00
Hawking Zhang
225cef9d88 drm/amdgpu: add nbio v2.3 for navi10 (v4)
nbio handles bus io functionality.

v1: add place holder and initial basic nbio v2.3 functions (Ray)
v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking)
v3: squash in updates (Alex)
v4: whitespace fix (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:18:36 -05:00
Leo Liu
b45ddfe811 drm/amdgpu: add nbio callbacks for vcn doorbell support
For Navi10 VCN2.0, the engine supports Doorbell

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
09fa0613bd drm/amdgpu: query vram_width from vram_info table
Driver will get channel_number and channel_width from
vram_info table, then calculate vram_width by multiply
channel_number by channel_width

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
89d7a79c7b drm/amdgpu: query vram type from atomfirmware vram_info
vram_type is saved in member vram_module[0].memory_type

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
98cd7f5b18 drm/amdgpu: add navi pm4 header
A pm4 header for Navi. PM4 is the packet format used
by the compute and gfx engines.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
9a87c32fda drm/amdgpu: add sdma v5 packet header file
Defines the SDMA packet formats.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Huang Rui
1f43631be5 drm/amdgpu: add gfx v10 clear state header v2
Clear state for gfx pipe.

v2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:37 -05:00
Hawking Zhang
35c2e91059 drm/amdgpu: parse the new members added by gpu_info ucode v1_1
Parse the new parameters for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:16 -05:00
Hawking Zhang
109c80ddb4 drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10
two new members that specific for navi10 are included in v2_0:
num_sc_per_sh and num_packer_per_sc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:11 -05:00
Huang Rui
23c6268eb1 drm/amdgpu: add navi10 gpu info firmware
gpu info firmware stores configuration data for various
IP blocks.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:15:29 -05:00
Hawking Zhang
3e514732c0 drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_override
New gfx config parameter.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:15:01 -05:00
Hawking Zhang
02a9e40a83 drm/amdgpu: add gfx10 specific config in amdgpu_gfx_config
The two members are used to cache the values from gpu_info fw accordingly

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:14:57 -05:00
Hawking Zhang
5228fe3010 drm/amdgpu: Add GDDR6 in vram_name arrary
For printing vram type.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:14:54 -05:00
Huang Rui
852a6626d5 drm/amdgpu: add navi10 asic type
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:56 -05:00
Hawking Zhang
76a2d0b0a1 drm/amdgpu: add doorbell assignement for navi10
Update mappings for Navi10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:51 -05:00
Jack Zhang
a95ecb653a drm/amdgpu/sriov: fix Tonga load driver failed
Tonga sriov need to use smu to load firmware.
Remove sriov flag because the default return value is zero.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Trigger Huang <Trigger.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:36:45 -05:00
Jonathan Kim
9c7c85f7ea drm/amdgpu: add pmu counters
adding perf event counters

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:36:22 -05:00
Jonathan Kim
e4cf4bf5b8 drm/amdgpu: update df_v3_6 for xgmi perfmons (v2)
add pmu attribute groups and structures for perf events.
add sysfs to track available df perfmon counters
fix overflow handling in perfmon counter reads.

v2: squash in fix (Alex)

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:35:45 -05:00
Philip Yang
e82fdb16a0 drm/amdgpu: improve HMM error -ENOMEM and -EBUSY handling
Under memory pressure, hmm_range_fault may return error code -ENOMEM
or -EBUSY, change pr_info to pr_debug to remove unnecessary kernel log
message because we will retry restore again.

Call get_user_pages_done if TTM get user pages failed will have
WARN_ONCE kernel calling stack dump log.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:33:41 -05:00
Tom St Denis
c1d827d62f drm/amd/amdgpu: cast mem->num_pages to 64-bits when shifting (v2)
On 32-bit hosts mem->num_pages is 32-bits and can overflow
when shifted.  Add a cast to avoid this.

(v2): Style fix.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:32:24 -05:00
xinhui pan
acb05f0a3f drm/amdgpu: Do error injection even vram reserve fails
As long as the address is mapped with vram, we can do an error
injection.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:32:10 -05:00
Daniel Vetter
52d2d44eee Merge v5.2-rc5 into drm-next
Maarten needs -rc4 backmerged so he can pull in the fbcon notifier
removal topic branch into drm-misc-next.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2019-06-19 12:07:29 +02:00
Alex Deucher
21a249ca02 drm/amdgpu: wait to fetch the vbios until after common init
We need the asic_funcs set for the get rom callbacks in some
cases.

Tested-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 11:02:03 -05:00
Arnd Bergmann
e1a2f2d23a drm/amdgpu: fix error handling in df_v3_6_pmc_start
When df_v3_6_pmc_get_ctrl_settings() fails for some reason, we
store uninitialized data in a register, as gcc points out:

drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function 'df_v3_6_pmc_start':
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1012:29: error: 'lo_val' may be used uninitialized in this function [-Werror=maybe-uninitialized]
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
                             ^~~~
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:334:39: note: 'lo_val' was declared here
  uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
                                       ^~~~~~

Make it return a proper error code that we can catch in the caller.

Fixes: 992af942a6 ("drm/amdgpu: add df perfmon regs and funcs for xgmi")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 11:02:03 -05:00
James Zhu
eb03e7959c drm/amdgpu: explicitly set mmGDS_VMID0_BASE to 0
Explicitly set mmGDS_VMID0_BASE to 0. Also update
GDS_VMID0_BASE/_SIZE with direct register writes.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 10:56:31 -05:00
Daniel Vetter
2454fcea33 Merge tag 'drm-misc-next-2019-06-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v5.3:

UAPI Changes:

Cross-subsystem Changes:
- Add code to signal all dma-fences when freed with pending signals.
- Annotate reservation object access in CONFIG_DEBUG_MUTEXES

Core Changes:
- Assorted documentation fixes.
- Use irqsave/restore spinlock to add crc entry.
- Move code around to drm_client, for internal modeset clients.
- Make drm_crtc.h and drm_debugfs.h self-contained.
- Remove drm_fb_helper_connector.
- Add bootsplash to todo.
- Fix lock ordering in pan_display_legacy.
- Support pinning buffers to current location in gem-vram.
- Remove the now unused locking functions from gem-vram.
- Remove the now unused kmap-object argument from vram helpers.
- Stop checking return value of debugfs_create.
- Add atomic encoder enable/disable helpers.
- pass drm_atomic_state to atomic connector check.
- Add atomic support for bridge enable/disable.
- Add self refresh helpers to core.

Driver Changes:
- Add extra delay to make MTP SDM845 work.
- Small fixes to virtio, vkms, sii902x, sii9234, ast, mcde, analogix, rockchip.
- Add zpos and ?BGR8888 support to meson.
- More removals of drm_os_linux and drmP headers for amd, radeon, sti, r128, r128, savage, sis.
- Allow synopsis to unwedge the i2c hdmi bus.
- Add orientation quirks for GPD panels.
- Edid cleanups and fixing handling for edid < 1.2.
- Add runtime pm to stm.
- Handle s/r in dw-hdmi.
- Add hooks for power on/off to dsi for stm.
- Remove virtio dirty tracking code, done in drm core.
- Rework BO handling in ast and mgag200.

Tiny conflict in drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c,
needed #include <linux/slab.h> to make it compile.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0e01de30-9797-853c-732f-4a5bd6e61445@linux.intel.com
2019-06-14 11:44:24 +02:00