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345 Commits

Author SHA1 Message Date
Aurabindo Pillai
b73b737f3d drm/amd/display: Add some missing register definitions 
[Why&How]
Add some missing register definitions and rearrange some others to
maintain consistency with related definitions.

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-15 18:08:28 -04:00
Asad Kamal
59070fd9cc drm/amdgpu: Add pci usage to nbio v7.9 
Add implementation to get pcie usage for nbio v7.9.

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-09 09:46:05 -04:00
Ben Li
85c391abd2 drm/amdgpu: add ih 6.1 registers 
Add new registers.

v2: updates (Alex)

Signed-off-by: Ben Li <ben.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-07 16:35:31 -04:00
Jonathan Kim
4504f14338 drm/amdgpu: setup hw debug registers on driver initialization 
Add missing debug trap registers references and initialize all debug
registers on boot by clearing the hardware exception overrides and the
wave allocation ID index.

The debugger requires that TTMPs 6 & 7 save the dispatch ID to map
waves onto dispatch during compute context inspection.
In order to correctly set this up, set the special reserved CP bit by
default whenever the MQD is initailized.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 12:34:56 -04:00
Lijo Lazar
a3ffabb250 drm/amdgpu: Disable interrupt tracker on NBIOv7.9 
Enabling nBIF interrupt history tracker prevents LCLK deep sleep,
hence disable it

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 10:45:23 -04:00
Hawking Zhang
2b80ffc2d8 drm/amdgpu: Add gc v9_4_3 ras error status registers 
GC v9_4_3 introduces UE|CE_ERR_STATUS_LO|HI to log
hardware errors

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 10:37:34 -04:00
Hawking Zhang
6c2bebfca4 drm/amdgpu: Add vcn/jpeg ras err status registers 
Add new ras error status registers introduced in
vcn v4_0_3 to log vcn and jpeg ras error.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 09:58:12 -04:00
Hawking Zhang
90cbee204e drm/amdgpu: Add mmhub v1_8_0 ras err status registers 
add new ras error status registers introduced in
mmhub v1_8_0 to log mmea and mm_cane ras err, including
MMEAx_UE|CE_ERR_STATUS_LO|HI
MM_CANE_UE|CE_ERR_STATUS_LO|HI

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 09:53:09 -04:00
Hawking Zhang
d90d90a197 drm/amdgpu: Add sdma v4_4_2 ras registers 
SDMA_UE_ERR_STATUS_HI|LO are introduced in v4_4_2
to replace SDMA_EDC_COUNTER/COUNTER2 registers to
log SDMA RAS errors

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 09:52:57 -04:00
Hawking Zhang
63121b11a9 drm/amdgpu: add smuio v13_0_3 ip headers 
Add smuio v13_0_3 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 09:48:30 -04:00
Hawking Zhang
50b8b62ea4 drm/amdgpu: add vcn v4_0_3 ip headers 
Add vcn v4_0_3 register offset adn shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-06-09 09:40:50 -04:00
Mukul Joshi
318e431b30 drm/amdgpu: Enable IH retry CAM on GFX9 
This patch enables the IH retry CAM on GFX9 series cards. This
retry filter is used to prevent sending lots of retry interrupts
in a short span of time and overflowing the IH ring buffer. This
will also help reduce CPU interrupt workload.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-04-13 00:14:08 -04:00
Hawking Zhang
8e7a49e09e drm/amdgpu: add mmhub v1_8_0 ip headers 
Add mmhub v1_8_0 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-31 11:18:43 -04:00
Hawking Zhang
b11e193093 drm/amdgpu: add gc v9_4_3 ip headers 
Add gc v9_4_3 register offset and shift masks
header files

v2: update headers (Alex)
v3: more updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-31 11:18:43 -04:00
Hawking Zhang
40a9634b4f drm/amdgpu: add osssys v4_4_2 ip headers 
Add osssys v4_4_2 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-31 11:18:43 -04:00
Hawking Zhang
1b0f0f7b8b drm/amdgpu: add athub v1_8_0 ip headers 
Add athub v1_8_0 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-31 11:18:43 -04:00
Hawking Zhang
52b36510a1 drm/amdgpu: add nbio v7_9_0 ip headers 
Add nbio v7_9_0 register offset and shift masks
header files

v2: update headers (Alex)
v3: squash in updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-31 11:18:42 -04:00
Tom St Denis
67f3c20969 drm/amd/amdgpu: Add missing INT_STAT_DEBUG registers to GC 10.1 and 10.3 headers 
Checked against database, copied from GC 9.4.2 header.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-13 17:15:23 -04:00
Hawking Zhang
3e22193d8c drm/amdgpu: add mp v13_0_6 ip headers 
Add mp v13_0_6 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-07 14:22:41 -05:00
Hawking Zhang
fbf46565c6 drm/amdgpu: add sdma v4_4_2 ip headers 
Add sdma v4_4_2 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-07 14:21:57 -05:00
Hawking Zhang
4f17289f14 drm/amdgpu: add hdp v4_4_2 ip headers 
Add hdp v4_4_2 register offset and shift masks
header files

v2: update headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-03-07 14:21:56 -05:00
Stanley.Yang
442d61af79 drm/amdgpu: correct query xgmi3x16 pcs error status 
There is xgmi3x16 pcs error status for aldebaran, driver should
check xgmi3x16 pcs error status field instead of gopx16 pcs error
status field.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-01-17 16:11:52 -05:00
YiPeng Chai
79d949a2d6 amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers 
V2:
   Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register
   offset and shift masks.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-01-17 16:11:50 -05:00
Candice Li
6c03a3fc91 drm/amdgpu: Add df v4_3 headers 
Add df v4_3 header files.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-12-15 12:19:22 -05:00
Alex Deucher
e93e075d34 drm/amdgpu: add missing license to some files 
The driver is MIT, so add the licenses.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2265
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-11-23 10:31:31 -05:00
Tao Zhou
88733d6801 drm/amdgpu: add register definition for VCN RAS initialization 
Prepare for enableing VCN RAS poison.

v2: move SHIFT and MASK definitions to related sh_mask.h file.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-11-23 10:31:31 -05:00
Candice Li
6dddc1eb96 drm/amdgpu: Update umc v8_10_0 headers 
Add GeccCtrl offset and mask to umc v8_10_0 headers.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-10-11 11:05:35 -04:00
Tom St Denis
82806c25d5 drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.1 
These are used by umr to sort the hive nodes since the kernel
initializes the nodes in order of bus enumeration not XGMI hive
enumeration.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-09-29 09:41:43 -04:00
Tom St Denis
1ed1f6be6e drm/amd/amdgpu: update GC 10.3.0 pwrdec 
The 10.3 GC headers were missing most of the pwrdec block.
This patch adds the registers and bits present in the 10.1 header
but based on the contents of the 10.3 specs.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-09-13 12:54:23 -04:00
Tom St Denis
780244a2fe drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers 
The TCC_DISABLE registers were not included in the 10.3 headers and
instead just placed directly in the gfx_v10_0.c source.  This patch
adds them to the headers so tools like umr can scan them and support them.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-09-07 22:28:42 -04:00
Frank Min
a40a92af46 drm/amdgpu: add gc v11_0_3 ip headers 
Add gc v11_0_3 register offset and shift masks
header files

v2: update registers (Alex)

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-08-30 16:36:42 -04:00
Tim Huang
6575eb930d drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0 
Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-08-22 16:47:09 -04:00
Victor Zhao
bfaced6ee7 drm/amdgpu: save and restore gc hub regs 
Save and restore gfxhub regs as they will be reset during mode 2

Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-08-16 18:14:31 -04:00
Xiaojian Du
492af34c9f drm/amdgpu: add header files for MP 13.0.4 
This patch will add header files for MP 13.0.4.

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-29 15:24:38 -04:00
Chengming Gui
7c8e4a2572 drm/amd/amdgpu: add additional page fault settings for gfx11 
Add three additional page fault settings.

V2: move reg offset definition to header file. (Alex)
V3: add all shift/mask definitions of used reg. (Hawking)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-28 16:19:59 -04:00
YiPeng Chai
75510fac07 drm/amdgpu: add umc v8_10_0 ip headers 
Add umc v8_10_0 register offset and shift masks
header files

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-18 16:37:38 -04:00
Roman Li
8955ff11f5 drm/amdgpu: Add reg headers for DCN314 
Register headers for the following IPs:
- DCN  3.1.4
- DPCS 3.1.4

v2:(squash) clean up (Alex)

Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-13 20:57:04 -04:00
Alex Deucher
0a94608f0f drm/amdgpu: fix file permissions on some files 
Drop execute.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2085
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-13 11:25:18 -04:00
Alan Liu
7c50a3e99a drm/amd/display: Program ACP related register 
- Setup the shift and mask of HDMI_ACP_SEND register
- Program the register in hdmi stream encoder
- Also update ACP register in azalia configuration

Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-05 16:13:18 -04:00
Rodrigo Siqueira
e72f03f4bd drm/amd/display: Add missing registers for ACP 
We are missing some ACP registers/mask value for some specific ASICs.
This commit includes it to those ASICs that support it.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-07-05 16:10:28 -04:00
Aurabindo Pillai
262236b4f5 drm/amd/display: add missing reg defs for DCN3x HUBBUB 
[Why&How]
The omitted register definition caused call traces like:

[    3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu]
[    3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks
[    3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132
[    3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019
[    3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu]
[    3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f
[    3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246
[    3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000
[    3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650
[    3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658
[    3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0
[    3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718
[    3.811631] FS:  00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000
[    3.811634] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0
[    3.811637] Call Trace:
[    3.811640]  <TASK>
[    3.811642]  generic_reg_update_ex+0x69/0x200 [amdgpu]
[    3.811831]  ? _printk+0x58/0x6f
[    3.811836]  dcn32_init_crb+0x18f/0x1b0 [amdgpu]
[    3.812031]  dcn32_init_hw+0x379/0x6a0 [amdgpu]
[    3.812223]  dc_hardware_init+0xba/0x100 [amdgpu]
[    3.812415]  amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu]
[    3.812616]  ? dev_vprintk_emit+0x139/0x15d
[    3.812621]  ? dev_printk_emit+0x4e/0x65
[    3.812624]  dm_hw_init+0x12/0x30 [amdgpu]
[    3.812820]  amdgpu_device_init.cold+0x130d/0x178c [amdgpu]
[    3.813017]  ? pci_read_config_word+0x25/0x40
[    3.813021]  amdgpu_driver_load_kms+0x1a/0x130 [amdgpu]
[    3.813178]  amdgpu_pci_probe+0x130/0x330 [amdgpu]

Fixes: 4f29f9cf09 ("drm/amd: add register headers for DCN32/321")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-06-21 18:17:22 -04:00
Evan Quan
62f8f5c3bf drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0 
Enable ASPM support for PCIE 7.4.0 and 7.6.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-06-08 11:43:00 -04:00
Alan Liu
8b67e738ca drm/amdgpu/display/dc: Add ACP_DATA register 
Define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA
Define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK/SHIFT

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-06-03 16:45:01 -04:00
Xiaojian Du
cb12d72b42 drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0 
This patch will add CSDMA reg offsets for NBIO v7.7.0

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-06-03 16:44:15 -04:00
Huang Rui
d57716702d drm/amdgpu: add mmhub v3_0_1 headers 
Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-06-03 16:44:15 -04:00
Aurabindo Pillai
4f29f9cf09 drm/amd: add register headers for DCN32/321 
Add register headers for DCN 3.2.0 and 3.2.1.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-06-03 16:43:37 -04:00
Alan Liu
6880ed280e drm/amd/display: Add HDMI_ACP_SEND register 
Define HDMI_ACP_SEND register shift/mask.

Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-26 14:56:32 -04:00
Hawking Zhang
81570d6dc2 drm/amdgpu: add lsdma v6_0_0 ip headers 
Add lsdma v6_0_0 register offset and shift masks
header files

v2: squash in updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-10 17:53:11 -04:00
Andrey Grodzovsky
bce04f216d drm/amd/psp: Add C2P registers to mp_13_0_2 header 
Add additional registers.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-06 16:58:10 -04:00
Huang Rui
c4d1c905ba drm/amdgpu: add hdp v5_2_1 ip headers 
Add hdp v5.2.1 offset and shift mask ip header files.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-06 10:36:13 -04:00