bybrooklyn/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-04-18 14:53:58 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,394,982 Commits 1 Branch 927 Tags
6093a688a07da07808f0122f9aa2a3eed250d853
Commit Graph

15 Commits

Author SHA1 Message Date
Raviteja Laggyshetty
273532a0da dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoC 
Add Operation State Manager (OSM) L3 interconnect provider binding for
QCS615 SoC. As the OSM hardware in QCS615 and SM8150 are same,
added a family-level compatible for SM8150 SoC.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250819-talos-l3-icc-v3-1-04529e85dac7@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2025-09-12 13:53:43 +03:00
Raviteja Laggyshetty
a95571d8ff dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC 
Add Epoch Subsystem (EPSS) L3 interconnect provider binding for
QCS8300 SoC. As the EPSS hardware in QCS8300 and SA8775P are same,
added a family-level compatible for SA877P SoC. This shared fallback
compatible allows grouping of SoCs with similar hardware, reducing
the need to explicitly list each variant in the driver match table.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250711102540.143-2-raviteja.laggyshetty@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2025-07-18 17:54:58 +03:00
Raviteja Laggyshetty
289198fb51 dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P 
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
SA8775P SoCs.
The L3 instance on the SA8775P SoC is similar to those on SoCs
like SM8250 and SC7280. These SoCs use the PERF register instead
of L3_REG for programming the performance level, which is managed
in the data associated with the target-specific compatibles.
Since the hardware remains the same across all EPSS-supporting SoCs,
the generic compatible is retained for all SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Link: https://lore.kernel.org/r/20250415095343.32125-2-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2025-04-15 14:13:30 +03:00
Neil Armstrong
f56c1b6db5 dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible 
Document the OSM L3 found in the Qualcomm SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250110-topic-sm8650-ddr-bw-scaling-v1-1-041d836b084c@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2025-01-13 20:00:25 +02:00
Richard Acayan
cb8790102b dt-bindings: interconnect: OSM L3: add SDM670 compatible 
Add the compatible for the OSM L3 interconnect used in the Snapdragon
670.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230816230412.76862-7-mailingradian@gmail.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2023-08-22 01:08:55 +03:00
Konrad Dybcio
e0c35141f9 dt-bindings: interconnect: OSM L3: Add SM6375 CPUCP compatible 
SM6375 includes a CPUCP block responsible for managing different APSS-
related tasks, such as scaling the voltage and frequency of the
components within the ARM DSU cluster. Add a compatible for the L3 cache
DVFS scaler within.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-2-708b8191f7eb@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2023-04-05 11:29:59 +03:00
Konrad Dybcio
62a4545614 dt-bindings: interconnect: OSM L3: Add SM6350 OSM L3 compatible 
SM6350, similarly to SDM845, uses OSM hardware for L3 scaling.
Document it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104171643.1004054-1-konrad.dybcio@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2023-01-19 20:06:11 +02:00
Bjorn Andersson
c70edc0677 dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles 
Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20221111032515.3460-6-quic_bjorande@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2022-11-17 17:14:29 +02:00
Sibi Sankar
f5f1a977fe dt-bindings: Update Sibi Sankar's email address 
Update email address to the quicinc.com domain.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1654130923-18722-1-git-send-email-quic_sibis@quicinc.com
 2022-06-02 09:42:02 -05:00
Odelu Kukatla
3b47746cd7 dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1634812857-10676-2-git-send-email-okukatla@codeaurora.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2021-11-22 16:56:50 +02:00
Bjorn Andersson
13fa44c0b6 dt-bindings: interconnect: Add SC8180x to OSM L3 DT binding 
The Qualcomm SC8180x has an OSM L3, add compatible for this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210725025834.3941777-1-bjorn.andersson@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
 2021-08-09 15:17:13 +03:00
Sibi Sankar
c4877059e0 dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250 
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SM8250
SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200801123049.32398-5-sibis@codeaurora.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
 2020-09-08 16:29:01 +03:00
Sibi Sankar
768220bb41 dt-bindings: interconnect: Add OSM L3 DT binding on SM8150 
Add Operation State Manager (OSM) L3 interconnect provider binding on
SM8150 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200801123049.32398-2-sibis@codeaurora.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
 2020-09-08 16:29:01 +03:00
Sibi Sankar
ff3edec1c3 dt-bindings: interconnect: Add OSM L3 DT binding on SC7180 
Add OSM L3 interconnect provider binding on SC7180 SoCs.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200227105632.15041-5-sibis@codeaurora.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
 2020-03-03 19:02:52 +02:00
Sibi Sankar
7a077f7fda dt-bindings: interconnect: Add OSM L3 DT bindings 
Add bindings for Operating State Manager (OSM) L3 interconnect provider
on SDM845 SoCs.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200227105632.15041-3-sibis@codeaurora.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
 2020-03-03 19:02:52 +02:00