Claudiu Beznea
e372aee8c2
dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
...
Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost
identical to the one available in RZ/G2{L,UL}, the exception being some
core clocks as follows:
- The SD clock is composed of a mux and a divider, and the divider
has some limitations (div = 1 cannot be set if mux rate is 800MHz),
- There are 3 SD clocks,
- The OCTA and TSU clocks are specific to RZ/G3S,
- PLL1/4/6 are specific to RZ/G3S with its own computation formula.
Even with this RZ/G3S could use the same bindings as RZ/G2L.
Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse
Generator (CPG) core clocks, module clocks and resets were added.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com >
Acked-by: Rob Herring <robh@kernel.org >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/r/20230929053915.1530607-13-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2023-10-05 11:25:53 +02:00
Rob Herring
3267197782
dt-bindings: clock: Drop unneeded quotes
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Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com >
Reviewed-by: Linus Walleij <linus.walleij@linaro.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Acked-by: Stephen Boyd <sboyd@kernel.org >
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/r/20230322173549.3972106-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
2023-03-31 10:00:53 -05:00
Lad Prabhakar
e312ae9207
dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
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The CPG block on the RZ/Five SoC is almost identical to one found on the
RZ/G2UL SoC. "renesas,r9a07g043-cpg" compatible string will be used on
the RZ/Five SoC so to make this clear, update the comment to include
RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2022-09-02 10:47:30 +02:00
Geert Uytterhoeven
fc9e01676c
dt-bindings: clock: renesas,rzg2l: Simplify header file references
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The bindings already uses <dt-bindings/clock/r9a0*-cpg.h> to refer to
the header files with DT binding definitions for core clocks.
Use more wildcards to simplify more references to these files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Acked-by: Rob Herring <robh@kernel.org >
Link: https://lore.kernel.org/r/f274ad16010798dd4a45d2dca5f870da8acbb470.1654696009.git.geert+renesas@glider.be
2022-06-13 11:53:18 +02:00
Phil Edworthy
4a526957e6
dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
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Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com >
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org >
Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2022-05-05 12:10:53 +02:00
Biju Das
3733db1f77
dt-bindings: clock: renesas: Document RZ/G2UL SoC
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Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Reviewed-by: Rob Herring <robh@kernel.org >
Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2022-04-04 10:58:46 +02:00
Biju Das
678eb67513
dt-bindings: clock: renesas: Document RZ/V2L SoC
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Document the device tree binding for the Renesas RZ/V2L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Acked-by: Rob Herring <robh@kernel.org >
Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2022-02-02 09:09:25 +01:00
Lad Prabhakar
f8ec89126a
dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
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Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Rob Herring <robh@kernel.org >
Link: https://lore.kernel.org/r/20210609153230.6967-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2021-06-10 15:46:00 +02:00
