Commit Graph

1885 Commits

Author SHA1 Message Date
Bjorn Andersson
0832b1c9d0 Merge branch '20230608125315.11454-2-srinivas.kandagatla@linaro.org' into arm64-for-6.5
Merge the SC8280XP LPASSCC DeviceTree bindings in order to get access
to the newly added reset defines.
2023-06-13 11:12:02 -07:00
Srinivas Kandagatla
83da70da40 dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset
support when it is under the control of Q6DSP.

Add support for those resets and adds IDs for clients to request the reset.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230608125315.11454-3-srinivas.kandagatla@linaro.org
2023-06-13 11:11:27 -07:00
Srinivas Kandagatla
bfc43a9c0c dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
The LPASS (Low Power Audio Subsystem) clock controller provides reset
support when it is under the control of Q6DSP.

Add support for those resets and adds IDs for clients to request the reset.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230608125315.11454-2-srinivas.kandagatla@linaro.org
2023-06-13 11:11:27 -07:00
Bjorn Andersson
68017e6b1b Merge branch '20230512122347.1219-3-quic_tdas@quicinc.com' into arm64-for-6.5
Merge the SDX75 GCC DeviceTree binding, in order to get access to the
clock defines in the DeviceTree source.
2023-06-13 11:06:07 -07:00
Luca Weiss
5683f11aa1 dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226
Define clock/clock-names properties of the MMCC device node to be used
on MSM8226 platform.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509-msm8226-mmcc-parents-v1-2-83a2dfc986ab@z3ntu.xyz
2023-06-13 10:02:57 -07:00
Alexander Stein
6e6bb16391 dt-bindings: clock: imx8m: Add missing interrupt property
All i.MX8M SoC have 2 CCM interrupts, called:
* Interrupt Request 1
* Interrupt Request 2

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230510065644.1317577-1-alexander.stein@ew.tq-group.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-06-12 12:16:09 +03:00
Damien Le Moal
f7efdf5e4d dt-bindings: Change Damien Le Moal's contact email
Change my email address to dlemoal@kernel.org.

Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Link: https://lore.kernel.org/r/20230514222614.115299-1-dlemoal@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-08 07:31:27 -06:00
Jacky Huang
2f8b5eb589 dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller
Add the dt-bindings header for Nuvoton ma35d1, that gets shared
between the clock controller and clock references in the dts.
Add documentation to describe nuvoton ma35d1 clock driver.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-05 13:18:08 +02:00
Michal Simek
a5e0a69dc3 dt-bindings: xilinx: Remove Rajan, Jolly and Manish
Rajan, Jolly and Manish are no longer work for AMD/Xilinx and there is no
activity from them to continue to maintain bindings that's why remove them.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b252dd71c82593fa6b137eca2174d9ab6e57f7a.1684828606.git.michal.simek@amd.com
2023-06-05 13:17:36 +02:00
Michal Simek
d5c421d24d dt-bindings: xilinx: Switch xilinx.com emails to amd.com
@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.

Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
2023-06-05 13:09:19 +02:00
Dmitry Rokosov
98872da6c6 dt-bindings: clock: meson: add A1 Peripherals clock controller bindings
Add documentation and dt bindings for the Amlogic A1 Peripherals clock
controller.
A1 PLL clock controller has references to A1 Peripherals clock
controller objects, so reflect them in the schema.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230523135351.19133-6-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-30 17:52:47 +02:00
Dmitry Rokosov
e6c6ddb397 dt-bindings: clock: meson: add A1 PLL clock controller bindings
Add the documentation and dt bindings for Amlogic A1 PLL clock
controller.
Also include new A1 clock controller dt bindings to MAINTAINERS.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230523135351.19133-4-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-30 17:52:42 +02:00
Bjorn Andersson
8368050625 Merge branch 'sm8450-sm8550-gpucc-binding' into arm64-for-6.5
Introduce DeviceTree bindings for SM8450 and SM8550 GPU clock
controller, to introduce the constants necessary to referr to these
clocks.
2023-05-26 18:27:58 -07:00
Bjorn Andersson
6de1bd7405 Merge branch 'sm8450-sm8550-gpucc-binding' into clk-for-6.5
Bring GPUCC DeviceTree bindings for SM8450 and SM8550 in through a topic
branch to allow sharing it with the DeviceTree source tree as well.
2023-05-26 18:22:17 -07:00
Jagadeesh Kona
778af143ad dt-bindings: clock: qcom: Add SM8550 graphics clock controller
Add device tree bindings for the graphics clock controller on
Qualcomm SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com
2023-05-26 18:22:07 -07:00
Konrad Dybcio
63f4e4b6f5 dt-bindings: clock: Add Qcom SM8450 GPUCC
Add device tree bindings for the graphics clock controller on Qualcomm
Technology Inc's SM8450 SoCs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org
2023-05-26 18:22:04 -07:00
Devi Priya
17035787e2 dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible
IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53
bindings as the PLL properties match with that of A53.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406061314.10916-2-quic_devipriy@quicinc.com
2023-05-26 12:16:40 -07:00
Krzysztof Kozlowski
7a52084ae1 dt-bindings: clock: qcom,gcc-sc7280: document CX power domain
The GCC clock controller needs CX power domain, at least according to
DTS:

  sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected)

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516105241.30091-3-krzysztof.kozlowski@linaro.org
2023-05-24 21:47:17 -07:00
Krzysztof Kozlowski
21a95637a3 dt-bindings: clock: qcom,gcc-sc7180: document CX power domain
The GCC clock controller needs CX power domain, at least according to
DTS:

  sc7180-trogdor-pompom-r3.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected)

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516105241.30091-2-krzysztof.kozlowski@linaro.org
2023-05-24 21:47:17 -07:00
Krzysztof Kozlowski
2310ab77f1 dt-bindings: clock: qcom,gcc-sm8250: add missing bi_tcxo_ao clock
The initial SM8250 GCC driver added in commit 3e5770921a ("clk: qcom:
gcc: Add global clock controller driver for SM8250") already consumed it
on the clock.  This fixes warnings like:

  sm8250-xiaomi-elish-csot.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too long

Fixes: 98394efb48 ("dt-bindings: clock: Add SM8250 GCC clock bindings")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516105241.30091-1-krzysztof.kozlowski@linaro.org
2023-05-24 21:47:17 -07:00
Imran Shaik
379d72721b dt-bindings: clock: qcom: Add RPMHCC for SDX75
Add compatible string for qcom RPMHCC for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-4-quic_tdas@quicinc.com
2023-05-24 21:47:17 -07:00
Bjorn Andersson
521302ca64 Merge branch '20230512122347.1219-3-quic_tdas@quicinc.com' into clk-for-6.5
Merge SDX75 Global Clock Controller DeviceTree binding through a topic
branch, to allow inclusion in DeviceTree source as well.
2023-05-24 21:47:17 -07:00
Krzysztof Kozlowski
2f9b209646 dt-bindings: clock: qcom,gcc-msm8953: split to separate schema
The Qualcomm MSM8953 GCC clock controller has clock inputs, thus
existing gcc-other.yaml was not describing it fully.  Move the binding
to its own schema file and document the clocks based on DTS.  Add driver
contributors as its maintainers.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230408143729.84097-1-krzysztof.kozlowski@linaro.org
2023-05-24 21:47:16 -07:00
Jagadeesh Kona
c7d91f26f0 dt-bindings: clock: qcom: Add SM8550 video clock controller
Add compatible string for SM8550 video clock controller.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-3-quic_jkona@quicinc.com
2023-05-24 21:47:16 -07:00
Bjorn Andersson
cc8d2cf5cd Merge branch '20230524140656.7076-2-quic_tdas@quicinc.com' into HEAD
Merge the SM8450 Video Clock Controller DeviceTree binding through a
topic branch, in order to be able to use the introduced constants in
changes on DeviceTree source branch as well.
2023-05-24 21:47:16 -07:00
Bjorn Andersson
6d6a98aaa7 Merge branch '20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org' into HEAD
Merge the Video Clock Controller DeviceTree bindings through a topic
branch, in order to be able to use the introduced constants in the
DeviceTree source branch as well.
2023-05-24 21:46:48 -07:00
Konrad Dybcio
2aae5eaa94 dt-bindings: clock: Add SM8350 VIDEOCC
SM8350, like most recent higher-end chips has a separate clock
controller block just for the Venus IP. Document it.

The binding was separated as the driver, unlike the earlier ones, doesn't
expect clock-names to keep it easier to maintain.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org
2023-05-24 21:46:09 -07:00
Taniya Das
1e910b2ba0 dt-bindings: clock: qcom: Add SM8450 video clock controller
Add device tree bindings for the video clock controller on Qualcomm
SM8450 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com
2023-05-24 21:43:04 -07:00
Imran Shaik
1c305ea86b dt-bindings: clock: qcom: Add GCC clocks for SDX75
Add support for qcom global clock controller bindings for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-3-quic_tdas@quicinc.com
2023-05-24 21:02:36 -07:00
Bjorn Andersson
de6d1f0c49 dt-bindings: clock: qcom: Accept power-domains for GPUCC
In many designs the power-domains provided by the GPU clock controller
are powered by some GFX rail, add power-domains as a valid property to
allow this to be specified.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230523010348.63043-1-quic_bjorande@quicinc.com
2023-05-23 05:35:44 -07:00
Claudiu Beznea
9a7b010116 dt-bindings: clocks: at91sam9x5-sckc: convert to yaml
Convert Atmel slow clock controller documentation to yaml.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230517094119.2894220-6-claudiu.beznea@microchip.com
2023-05-22 15:59:49 +03:00
Claudiu Beznea
fffc869be4 dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml
Convert Atmel PMC documentation to yaml. Along with it clock names
were adapted according to the current available device trees as
different controller versions accept different clock (some of them
have 3 clocks as input, some has 2 clocks as inputs and some with 2
input clocks uses different clock names).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230517094119.2894220-3-claudiu.beznea@microchip.com
2023-05-22 15:59:43 +03:00
Devi Priya
3f2c154e1b dt-bindings: clock: qcom,ipq9574-gcc: Add maintainer
Add Bjorn andersson to the maintainer's list.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230425084010.15581-3-quic_devipriy@quicinc.com
2023-05-17 19:41:46 -07:00
Artur Weber
5b40732af0 dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible
Support for the Exynos4212 SoC was originally dropped as there were
no boards using it. We will be adding a device that uses it, so add
back the relevant compatible.

Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20230501195525.6268-3-aweber.kernel@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-09 19:48:19 +02:00
Linus Torvalds
418d5c9831 Merge tag 'devicetree-fixes-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring:

 - Add Conor Dooley as a DT binding maintainer

 - Swap the order of parsing /memreserve/ and /reserved-memory nodes so
   that the /reserved-memory nodes which have more information are
   handled first

 - Fix some property dependencies in riscv,pmu binding

 - Update maintainers entries on a couple of bindings

* tag 'devicetree-fixes-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  MAINTAINERS: add Conor as a dt-bindings maintainer
  dt-bindings: perf: riscv,pmu: fix property dependencies
  dt-bindings: xilinx: Remove Naga from memory and mtd bindings
  of: fdt: Scan /memreserve/ last
  dt-bindings: clock: r9a06g032-sysctrl: Change maintainer to Fabrizio Castro
  dt-bindings: pinctrl: renesas,rzv2m: Change maintainer to Fabrizio Castro
  dt-bindings: pinctrl: renesas,rzn1: Change maintainer to Fabrizio Castro
  dt-bindings: i2c: renesas,rzv2m: Change maintainer to Fabrizio Castro
2023-05-05 13:27:59 -07:00
Linus Torvalds
e81507acdc Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
 "Nothing looks out of the ordinary in this batch of clk driver updates.

  There are a couple patches to the core clk framework, but they're all
  basically cleanups or debugging aids. The driver updates and new
  additions are dominated in the diffstat by Qualcomm and MediaTek
  drivers. Qualcomm gained a handful of new drivers for various SoCs,
  and MediaTek gained a bunch of drivers for MT8188. The MediaTek
  drivers are being modernized as well, so there are updates all over
  that vendor's clk drivers. There's also a couple other new clk drivers
  in here, for example the Starfive JH7110 SoC support is added.

  Outside of the two major SoC vendors though, we have the usual
  collection of non-critical fixes and cleanups to various clk drivers.
  It's good to see that we're getting more cleanups and modernization
  patches. Maybe one day we'll be able to properly split clk providers
  from clk consumers.

  Core:
   - Print an informational message before disabling unused clks

  New Drivers:
   - BCM63268 timer clock and reset controller
   - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
     MT8195 SoCs
   - Mediatek MT8188 SoC clk drivers
   - Clock driver for Sunplus SP7021 SoC
   - Clk driver support for Loongson-2 SoCs
   - Clock driver for Skyworks Si521xx I2C PCIe clock generators
   - Initial Starfive JH7110 clk/reset support
   - Global clock controller drivers for Qualcomm SM7150, IPQ9574,
     MSM8917 and IPQ5332 SoCs
   - GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P
     SoCs

  Updates:
   - Shrink size of clk_fractional_divider a little
   - Convert various clk drivers to devm_of_clk_add_hw_provider()
   - Convert platform clk drivers to remove_new()
   - Converted most Mediatek clock drivers to struct platform_driver
   - MediaTek clock drivers can be built as modules
   - Reimplement Loongson-1 clk driver with DT support
   - Migrate socfpga clk driver to of_clk_add_hw_provider()
   - Support for i3c clks on Aspeed ast2600 SoCs
   - Add clock generic devm_clk_hw_register_gate_parent_data
   - Add audiomix block control for i.MX8MP
   - Add support for determine_rate to i.MX composite-8m
   - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate
   - Provide clock name in error message for clk-gpr-mux on get parent
     failure
   - Drop duplicate imx_clk_mux_flags macro
   - Register the i.MX8MP Media Disp2 Pix clock as bus clock
   - Add Media LDB root clock to i.MX8MP
   - Make i.MX8MP nand_usdhc_bus clock as non-critical
   - Fix the rate table for i.MX fracn-gppll
   - Disable HW control for the fracn-gppll in order to be controlled by
     register write
   - Add support for interger PLL in fracn-gppll
   - Add mcore_booted module parameter to i.MX93 provider
   - Add NIC, A55 and ARM PLL clocks to i.MX93
   - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents
   - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP
     to get more accurate clock rates
   - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical
   - Update some of the i.MX critical clocks flags to allow glitchless
     on-the-fly rate change.
   - Add I2C5 clock on Renesas R-Car V3H
   - Exynos850: Add CMU_G3D clock controller for the Mali GPU
   - Extract Exynos5433 (ARM64) clock controller power management code
     to common driver parts
   - Exynos850: make PMU_ALIVE_PCLK clock critical
   - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel
     Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car
     V4H
   - Add video capture (VIN) clocks on Renesas R-Car V3H
   - Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H
   - Support for Stromer Plus PLL on Qualcomm IPQ5332
   - Add a missing reset to Qualcomm QCM2290
   - Migrate Qualcomm IPQ4019 to clk_parent_data
   - Make USB GDSCs enter retention state when disabled on Qualcomm
     SM6375, MSM8996 and MSM8998 SoCs
   - Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk
   - Add two EMAC GDSCs on Qualcomm SC8280XP
   - Use shared rcg clk ops in Qualcomm SM6115 GCC
   - Park Qualcomm SM8350 PCIe PIPE clks when disabled
   - Add GDSCs to Qualcomm SC7280 LPASS audio clock controller
   - Add missing XO clocks to Qualcomm MSM8226 and MSM8974
   - Convert some Qualcomm clk DT bindings to YAML
   - Reparenting fix for the clock supplying camera modules on Rockchip
     rk3399
   - Mark more critical (bus-)clocks on Rockchip rk3588"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits)
  clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
  clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
  clk: rockchip: rk3588: make gate linked clocks critical
  clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
  clk: qcom: add the GPUCC driver for sa8775p
  dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
  clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
  clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
  clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
  dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
  clk: starfive: Avoid casting iomem pointers
  clk: microchip: fix potential UAF in auxdev release callback
  clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
  clk: mediatek: fhctl: Mark local variables static
  clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
  clk: uniphier: Use managed `of_clk_add_hw_provider()`
  clk: si5351: Use managed `of_clk_add_hw_provider()`
  clk: si570: Use managed `of_clk_add_hw_provider()`
  clk: si514: Use managed `of_clk_add_hw_provider()`
  clk: lmk04832: Use managed `of_clk_add_hw_provider()`
  ...
2023-04-29 17:29:39 -07:00
Linus Torvalds
d42b1c4757 Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
     TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
     FPGA bindings to DT schema format

   - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
     controller

   - Add MediaTek MT8365 UART and SYSIRQ bindings

   - Add Arm Cortex-A78C and X1C core compatibles

   - Add vendor prefix for Novatek

   - Remove bindings for stih415, sti416, stid127 platforms

   - Drop uneeded quotes in schema files. This is preparation for
     yamllint checking quoting for us.

   - Add missing (unevaluated|additional)Properties constraints on child
     node schemas

   - Clean-up schema comments formatting

   - Fix I2C and SPI node bus names in schema examples

   - Clean-up some display compatibles schema syntax

   - Fix incorrect references to lvds.yaml

   - Gather all cache controller bindings in a common directory

  DT core:

   - Convert unittest to new void .remove platform device hook

   - kerneldoc fixes for DT address of_pci_range_to_resource/
     of_address_to_resource functions"

* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
  dt-bindings: rng: Drop unneeded quotes
  dt-bindings: arm/soc: mediatek: Drop unneeded quotes
  dt-bindings: soc: qcom: Drop unneeded quotes
  dt-bindings: i2c: samsung: Fix 'deprecated' value
  dt-bindings: display: Fix lvds.yaml references
  dt-bindings: display: simplify compatibles syntax
  dt-bindings: display: mediatek: simplify compatibles syntax
  dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
  dt-bindings: timer: Drop unneeded quotes
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
  dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
  dt-bindings: reset: remove stih415/stih416 reset
  dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
  dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
  dt-bindings: iommu: Convert QCOM IOMMU to YAML
  dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
  dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
  of: address: Reshuffle to remove forward declarations
  of: address: Fix documented return value of of_pci_range_to_resource()
  of: address: Document return value of of_address_to_resource()
  ...
2023-04-27 09:23:57 -07:00
Chris Paterson
6e0c2bf2ca dt-bindings: clock: r9a06g032-sysctrl: Change maintainer to Fabrizio Castro
Gareth no longer works for Renesas.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Acked-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230426100925.12063-1-chris.paterson2@renesas.com
Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-27 11:03:18 -05:00
Stephen Boyd
a9863979fb Merge branch 'clk-imx' into clk-next
* clk-imx: (25 commits)
  clk: imx: imx8ulp: update clk flag for system critical clock
  clk: imx: imx8ulp: Add tpm5 clock as critical gate clock
  clk: imx: imx8ulp: keep MU0_B clock enabled always
  clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
  clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents
  clk: imx: imx93: Add nic and A55 clk
  dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK
  clk: imx: imx93: add mcore_booted module paratemter
  clk: imx: fracn-gppll: Add 300MHz freq support for imx9
  clk: imx: fracn-gppll: support integer pll
  clk: imx: fracn-gppll: disable hardware select control
  clk: imx: fracn-gppll: fix the rate table
  clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical
  clk: imx: imx8mp: Add LDB root clock
  dt-bindings: clock: imx8mp: Add LDB clock entry
  clk: imx: imx8mp: correct DISP2 pixel clock type
  clk: imx: drop duplicated macro
  clk: imx: clk-gpr-mux: Provide clock name in error message
  clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
  clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
  ...
2023-04-25 11:52:39 -07:00
Stephen Boyd
c19c6c7b44 Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-of:
  clk: add missing of_node_put() in "assigned-clocks" property parsing

* clk-samsung:
  clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
  clk: samsung: Convert to platform remove callback returning void
  clk: samsung: exynos5433: Extract PM support to common ARM64 layer
  clk: samsung: Extract parent clock enabling to common function
  clk: samsung: Extract clocks registration to common function
  clk: samsung: exynos850: Add AUD and HSI main gate clocks
  clk: samsung: exynos850: Implement CMU_G3D domain
  clk: samsung: clk-pll: Implement pll0818x PLL type
  clk: samsung: Set dev in samsung_clk_init()
  clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
  clk: samsung: Remove np argument from samsung_clk_init()
  dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
  dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D

* clk-rockchip:
  clk: rockchip: rk3588: make gate linked clocks critical
  clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent

* clk-qcom: (57 commits)
  clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
  clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
  clk: qcom: add the GPUCC driver for sa8775p
  dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
  clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
  clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
  clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
  dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
  clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  dt-bindings: clock: Add ipq9574 clock and reset definitions
  clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
  clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
  clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
  dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
  clk: qcom: apss-ipq-pll: add support for IPQ5332
  dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
  clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
  dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
  dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
  ...
2023-04-25 11:52:25 -07:00
Stephen Boyd
1a86e99fa0 Merge branches 'clk-starfive', 'clk-fractional' and 'clk-devmof' into clk-next
- Shrink size of clk_fractional_divider a little
 - Convert various clk drivers to devm_of_clk_add_hw_provider()

* clk-starfive:
  clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
  clk: starfive: Avoid casting iomem pointers
  MAINTAINERS: generalise StarFive clk/reset entries
  reset: starfive: Add StarFive JH7110 reset driver
  clk: starfive: Add StarFive JH7110 always-on clock driver
  clk: starfive: Add StarFive JH7110 system clock driver
  reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
  reset: starfive: Rename "jh7100" to "jh71x0" for the common code
  reset: starfive: Extract the common JH71X0 reset code
  reset: starfive: Factor out common JH71X0 reset code
  reset: Create subdirectory for StarFive drivers
  reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
  clk: starfive: Rename "jh7100" to "jh71x0" for the common code
  clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
  clk: starfive: Factor out common JH7100 and JH7110 code
  clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
  dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

* clk-fractional:
  clk: Remove mmask and nmask fields in struct clk_fractional_divider
  clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider
  clk: imx: Remove values for mmask and nmask in struct clk_fractional_divider
  clk: Compute masks for fractional_divider clk when needed.

* clk-devmof:
  clk: uniphier: Use managed `of_clk_add_hw_provider()`
  clk: si5351: Use managed `of_clk_add_hw_provider()`
  clk: si570: Use managed `of_clk_add_hw_provider()`
  clk: si514: Use managed `of_clk_add_hw_provider()`
  clk: lmk04832: Use managed `of_clk_add_hw_provider()`
  clk: hsdk-pll: Use managed `of_clk_add_hw_provider()`
  clk: cdce706: Use managed `of_clk_add_hw_provider()`
  clk: axs10x: Use managed `of_clk_add_hw_provider()`
  clk: axm5516: Use managed `of_clk_add_hw_provider()`
  clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`
2023-04-25 11:50:49 -07:00
Stephen Boyd
caca6ad367 Merge branches 'clk-xilinx', 'clk-broadcom' and 'clk-platform' into clk-next
- BCM63268 timer clock and reset controller
 - Convert platform clk drivers to remove_new

* clk-xilinx:
  clocking-wizard: Support higher frequency accuracy
  clk: zynqmp: pll: Remove the limit

* clk-broadcom:
  clk: bcm: Add BCM63268 timer clock and reset driver
  dt-bindings: clock: Add BCM63268 timer binding
  dt-bindings: reset: add BCM63268 timer reset definitions
  dt-bindings: clk: add BCM63268 timer clock definitions

* clk-platform: (25 commits)
  clk: xilinx: Convert to platform remove callback returning void
  clk: x86: Convert to platform remove callback returning void
  clk: uniphier: Convert to platform remove callback returning void
  clk: ti: Convert to platform remove callback returning void
  clk: tegra: Convert to platform remove callback returning void
  clk: stm32: Convert to platform remove callback returning void
  clk: mvebu: Convert to platform remove callback returning void
  clk: mmp: Convert to platform remove callback returning void
  clk: keystone: Convert to platform remove callback returning void
  clk: hisilicon: Convert to platform remove callback returning void
  clk: stm32mp1: Convert to platform remove callback returning void
  clk: scpi: Convert to platform remove callback returning void
  clk: s2mps11: Convert to platform remove callback returning void
  clk: pwm: Convert to platform remove callback returning void
  clk: palmas: Convert to platform remove callback returning void
  clk: hsdk-pll: Convert to platform remove callback returning void
  clk: fixed-rate: Convert to platform remove callback returning void
  clk: fixed-mmio: Convert to platform remove callback returning void
  clk: fixed-factor: Convert to platform remove callback returning void
  clk: axm5516: Convert to platform remove callback returning void
  ...
2023-04-25 11:50:36 -07:00
Stephen Boyd
6f7478e3bb Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
   MT8195 SoCs
 - Converted most Mediatek clock drivers to struct platform_driver
 - MediaTek clock drivers can be built as modules
 - Mediatek MT8188 SoC clk drivers
 - Clock driver for Sunplus SP7021 SoC
 - Reimplement Loongson-1 clk driver with DT support
 - Clk driver support for Loongson-2 SoCs
 - Migrate socfpga clk driver to of_clk_add_hw_provider()

* clk-mediatek: (84 commits)
  clk: mediatek: fhctl: Mark local variables static
  clk: mediatek: Use right match table, include mod_devicetable
  clk: mediatek: Add MT8188 adsp clock support
  clk: mediatek: Add MT8188 imp i2c wrapper clock support
  clk: mediatek: Add MT8188 wpesys clock support
  clk: mediatek: Add MT8188 vppsys1 clock support
  clk: mediatek: Add MT8188 vppsys0 clock support
  clk: mediatek: Add MT8188 vencsys clock support
  clk: mediatek: Add MT8188 vdosys1 clock support
  clk: mediatek: Add MT8188 vdosys0 clock support
  clk: mediatek: Add MT8188 vdecsys clock support
  clk: mediatek: Add MT8188 mfgcfg clock support
  clk: mediatek: Add MT8188 ipesys clock support
  clk: mediatek: Add MT8188 imgsys clock support
  clk: mediatek: Add MT8188 ccusys clock support
  clk: mediatek: Add MT8188 camsys clock support
  clk: mediatek: Add MT8188 infrastructure clock support
  clk: mediatek: Add MT8188 peripheral clock support
  clk: mediatek: Add MT8188 topckgen clock support
  clk: mediatek: Add MT8188 apmixedsys clock support
  ...

* clk-sunplus:
  clk: Add Sunplus SP7021 clock driver

* clk-loongson:
  clk: clk-loongson2: add clock controller driver support
  dt-bindings: clock: add loongson-2 boot clock index
  MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
  MIPS: loongson32: Update the clock initialization
  clk: loongson1: Re-implement the clock driver
  clk: loongson1: Remove the outdated driver
  dt-bindings: clock: Add Loongson-1 clock

* clk-socfpga:
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
2023-04-25 11:50:08 -07:00
Stephen Boyd
4ec6a2f957 Merge branches 'clk-cleanup', 'clk-aspeed', 'clk-dt', 'clk-renesas' and 'clk-skyworks' into clk-next
- Support for i3c clks on Aspeed ast2600 SoCs
 - Clock driver for Skyworks Si521xx I2C PCIe clock generators

* clk-cleanup:
  clk: microchip: fix potential UAF in auxdev release callback
  clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
  clk: stm32h7: Remove an unused field in struct stm32_fractional_divider
  clk: tegra20: fix gcc-7 constant overflow warning
  clock: milbeaut: use devm_platform_get_and_ioremap_resource()
  clk: Print an info line before disabling unused clocks
  clk: ti: Use of_address_to_resource()
  clk: remove unnecessary (void*) conversions
  clk: at91: clk-sam9x60-pll: fix return value check
  clk: visconti: remove unused visconti_pll_provider::regmap

* clk-aspeed:
  dt-bindings: clock: ast2600: Expand comment on reset definitions
  clk: ast2600: Add comment about combined clock + reset handling
  dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions
  clk: ast2600: Add full configs for I3C clocks
  dt-bindings: clock: ast2600: Add top-level I3C clock
  clk: ast2600: allow empty entries in aspeed_g6_gates

* clk-dt:
  clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt()
  clk: Use of_property_present() for testing DT property presence

* clk-renesas:
  clk: renesas: r8a77980: Add I2C5 clock
  clk: rs9: Add support for 9FGV0441
  clk: rs9: Support device specific dif bit calculation
  dt-bindings: clk: rs9: Add 9FGV0441
  clk: rs9: Check for vendor/device ID
  clk: renesas: Convert to platform remove callback returning void
  clk: renesas: r9a06g032: Improve clock tables
  clk: renesas: r9a06g032: Document structs
  clk: renesas: r9a06g032: Drop unused fields
  clk: renesas: r9a06g032: Improve readability
  clk: renesas: r8a77980: Add Z2 clock
  clk: renesas: r8a77970: Add Z2 clock
  clk: renesas: r8a77995: Fix VIN parent clock
  clk: renesas: r8a77980: Add VIN clocks
  clk: renesas: r8a779g0: Add VIN clocks
  clk: renesas: r8a779g0: Add ISPCS clocks
  clk: renesas: r8a779g0: Add CSI-2 clocks
  clk: renesas: r8a779g0: Add thermal clock
  clk: renesas: r8a779g0: Add Audio clocks
  clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H

* clk-skyworks:
  clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators
  dt-bindings: clk: si521xx: Add Skyworks Si521xx I2C PCIe clock generators
2023-04-25 11:49:50 -07:00
Arnd Bergmann
718acce6f0 Merge tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
More Qualcomm ARM64 Devicetree updated for v6.4

Devicetree for the QCM2210/QCM2290 is introduced. Support for the RB1
board is introduced on QRB2210, RB2 on QRB4210, the AL02 board on
IPQ9574, the MI01.6 board is introduced on IPQ5332 and initial support
for Xiaomi Mi A3 is introduced on SM6125.

Support for the output-enable/disable flag is introduced in the
pinctrl-msm driver, and the non-standard "input-enable" is dropped from
a range of platforms.

A wide range of smaller fixes are introduced, based on Devicetree
validation.

MSM8953 gains LPASS, MPSS and Wireless subsystem support.

The iommus property is removed from PCIe nodes in all platforms, as the
only the child devices should be associated with iommu groups, through
the existing iommu-map property.

A few QUP instances are introduced on the IPQ5332 platform, and support
for the MI01.6 board is introduced.

The reserved-memory map on Huawei Nexus 6P is updated with the addition
of splash screen framebuffer memory and adjustment to the reserved
memory region overlapping the smem region.

Regulators are introduces for the SA8775P Ride platform.

A regulator is marked always-on, for correctness, on Trogdor. Pinconf
fixes are introduced to both sc7180 and sc7280 devices. A dedicated
reviewers list is added for boards relevant to the Chromebook engineers.

A set of pinconf fixes are introduced for sc8280xp, labels are
introduced for Soundwire nodes.

The sensor core remoteproc and FastRPC thereon, is introduce in SDM845
and enabled for OnePlus 6/6T and Shift Shift6mq.

RMTFS, remoteprocs, ath10k and ramoops is introduced for the Lenovo Tab
P11.

UFS support is introduced on SM6125.

SM8150 no longer defines the GPU to be in headless mode by default, GPU
speedbins are introduced.

GPU speedbins are introduced for SM8250 as well, as is support for
display on Xiaomi Mi Pad 5 Pro, with two different panels supported.

Soundwire controllers, ADSP audio codec macros and the Inline Crypto
Engine support is added to the SM8550 platform.

* tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (85 commits)
  arm64: dts: qcom: Add base qrb4210-rb2 board dts
  arm64: dts: qcom: sm8550: add Soundwire controllers
  arm64: dts: qcom: sm8250: Add GPU speedbin support
  arm64: dts: qcom: sm8150: Add GPU speedbin support
  arm64: dts: qcom: sm8150: Don't start Adreno in headless mode
  arm64: dts: qcom: ipq5332: add support for the RDP468 variant
  arm64: dts: qcom: sdm630: move DSI opp-table out of DSI node
  arm64: dts: qcom: sm6115p-j606f: Enable ATH10K WiFi
  arm64: dts: qcom: sm6115p-j606f: Enable remoteprocs
  arm64: dts: qcom: sm6115: Add RMTFS
  arm64: dts: qcom: sm6115-j606f: Add ramoops node
  arm64: dts: qcom: msm8916-thwc-ufi001c: add function to pin config
  arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node
  arm64: dts: MSM8953: Add lpass nodes
  arm64: dts: MSM8953: Add mpss nodes
  arm64: dts: MSM8953: Add wcnss nodes
  arm64: dts: qcom: sm8350: remove superfluous "input-enable"
  arm64: dts: qcom: sm8150: remove superfluous "input-enable"
  arm64: dts: qcom: apq8016: remove superfluous "input-enable"
  arm64: dts: qcom: sc8280xp-lenovo-thinkpad: correct pin drive-strength
  ...

Link: https://lore.kernel.org/r/20230414031550.2412379-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-14 18:01:50 +02:00
Arnd Bergmann
10678a0751 Merge tag 'qcom-arm64-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 updates for v6.4

PCI I/O and MEM ranges are corrected across all targets with PCIe
enabled. Likewise is CPU clocks defined to be provided from CPUfreq for
a wide range of platforms, to satisfy the OPP definitions, and LLCC bank
information is corrected for all relevant platforms.

IPQ5332 gains SMEM, CPUfreq and support for triggering download mode.
The MI01.2 board is introduced.

On MSM8916 WCN compatibles are moved to be defined per board, to avoid
issues when boards rely on the incorrect defaults. Support for Yiming
UZ801 4G modem stick is introduced.

XO clock is defined and fed to RPMCC on MSM8953 and MSM8976, to ensure
clock trees are properly rooted. DSI clocks feeding into gcc are
described on MSM8953.

On MSM8996 the external audio components are moved from the SoC dtsi. A
few DWC3 quirks are added.

On MSM8998 GPIO names are introduced for Sony Xperia XZ Premium, XZ1 and
XZ1 Compact. A numbe of boards have GPIO keys properly marked as
wakeup-source.

The SA8775P platform is extended with CPUfreq, UARTs, I2C controllers,
SPI controllers, SPMI and PMICs, PDC support. The associated PMICs gains
reset and power key support, as well as thermal zones defined. Nodes are
sorted. On top of this the SA8775P Ride board/platform is introduced.

On SC7180 and SC7280 a range of fixes coming from DeviceTree validation are
introduced, some clearing up unused properties, others correcting
errors. A number of Google rev0 boards on SC7180 are dropped, as these
are not considered to be in use by anyone anymore.

On SC8280XP RTC support is introduced and enabled for the CRD and Lenovo
Thinkpad X13s. It gains another UART, upon which Bluetooth is enabled on
the Lenovo ThinkPad X13s. The touchpad definition is altered to attempt
to probe both devices seen in the wild. A number of bug fixes are also
introduced, and the regulator definitions on X13s are corrected.

On SDM845 dynamic power coefficients are improved. BWMON compatible is
corrected. Xiaomi Pocophone F1 gains notification LED. Sony Xperia XZ2,
XZ2 Compact and XZ3 gains display, touchscreen, gpu and remoteproc
support. OnePlus 6 and 6T gains hall sensor.

GPU clock controller and remoteproc nodes are added for SM6115. CPU
clock are defined to come from CPUfreq. Board-specific USB-properties
are moved out of the SoC dtsi.

On SM6375 L3 scaling, IMEM, RMTFS, RPM sleep stats, Tsens, modem
remoteproc and WiFi nodes are added. Tsens thermal zones are defined and additional low power states
are defined. Sony Xperia 10 IV gains volume down key support.

On SM8150 another UART is introduced, to be used by GNSS on the SA8155
ADP. Support for the Flash LED block in PM8150L is added.

On SM8250 TPDM MM and PRNG is defined, MHI region is added to PCIe node.
A few bug fixes are introduced after Devicetree validation.

The DisplayPort controller on both SM8350 and SM8450 is defined and the
related QMP instance is transitioned to the USB3/DP combo variant. IMEM
and PIL info is introduced, for post mortem debugging of remoteprocs. On
the HDK PMIC GLINK is enabled and role switch is enabled. Some audio
resources are corrected.

A typo in the USB role property of the Microsoft Surface is corrected,
thanks to DeviceTree validation.

PCIe controllers and PHYs descriptions are corrected, and pinctrl state
definitions are moved from the soc to the board definition. BWMON
compatibles are corrected. PM8550B gains the definition of the eUSB2
repeater and this is enabled on the MTP. PMIC GLINK is also defined for
the MTP and connected to DWC3, for role switching support.

In addition to this, a range of cleanups based on Devicetree validation
is introduced.

A few clock bindings are introduced, from topic-branches shared with the
clock tree, to aid introduction of references to these.

* tag 'qcom-arm64-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (256 commits)
  arm64: dts: qcom: sc8280xp-x13s: Add bluetooth
  arm64: dts: qcom: sc8280xp: Define uart2
  arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
  arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
  arm64: dts: qcom: sa8775p: pmic: add thermal zones
  arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
  arm64: dts: qcom: sa8775p: pmic: add the power key
  arm64: dts: qcom: sa8775p: add the Power On device node
  arm64: dts: qcom: sa8775p: add support for the on-board PMICs
  arm64: dts: qcom: sa8775p: add the spmi node
  arm64: dts: qcom: sa8775p: add the pdc node
  arm64: dts: qcom: sa8775p: sort soc nodes by reg property
  arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
  arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name
  arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1
  arm64: dts: qcom: sdm845-tama: Enable GPU
  arm64: dts: qcom: sdm845-tama: Enable remoteprocs
  ...

Link: https://lore.kernel.org/r/20230410170233.5931-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-14 17:57:17 +02:00
Arnd Bergmann
d40a2f5062 Merge tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.4

Microchip:
A "fix" for the system controller's regs on PolarFire SoC, adding a
missing reg property.
The patch had been sitting there for months and I only re-found it
recently, so you can guess how much of a "fix" it actually is. It'll
become needed when the system controller's QSPI gets added in the future,
but at present there's no urgency as the driver can handle both the
current and "fixed" versions.

StarFive:
Basic support for the JH7110 & the associated first-party dev board, the
VisionFive v2 (in two forms). There's a bunch of dt-bindings required
for this too, all of which have had input from the DT folk. There's
enough in this tag to boot to a console w/ an initramfs but little more.
The SoC supports some of the "new" bit manipulation instructions, which
is a good test for the recently added Zbb support in the kernel.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
  riscv: dts: starfive: Add StarFive JH7110 pin function definitions
  riscv: dts: starfive: Add initial StarFive JH7110 device tree
  dt-bindings: riscv: Add SiFive S7 compatible
  dt-bindings: interrupt-controller: Add StarFive JH7110 plic
  dt-bindings: timer: Add StarFive JH7110 clint
  dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
  riscv: dts: microchip: fix the mpfs' mailbox regs
  riscv: dts: microchip: add mpfs specific macb reset support

Link: https://lore.kernel.org/r/20230406-shank-impromptu-3d483bbc249f@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-14 15:24:00 +02:00
Arnd Bergmann
295954fefe Merge tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux into soc/dt
Apple SoC DT updates for 6.4.

This time we have the M2 (t8112) device trees and compatible updates,
as well as a minor fix for PCIe ports on the prior models.

* tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux:
  arm64: dts: apple: t600x: Disable unused PCIe ports
  arm64: dts: apple: t8103: Disable unused PCIe ports
  arm64: dts: apple: t8112: Initial t8112 (M2) device trees
  dt-bindings: arm: apple: Add t8112 j413/j473/j493 compatibles
  dt-bindings: clock: apple,nco: Add t8112-nco compatible
  dt-bindings: i2c: apple,i2c: Add apple,t8112-i2c compatible
  dt-bindings: pinctrl: apple,pinctrl: Add apple,t8112-pinctrl compatible
  dt-bindings: pci: apple,pcie: Add t8112 support
  dt-bindings: nvme: apple: Add apple,t8112-nvme-ans2 compatible string
  dt-bindings: mailbox: apple,mailbox: Add t8112 compatibles
  dt-bindings: iommu: apple,sart: Add apple,t8112-sart compatible string
  dt-bindings: interrupt-controller: apple,aic2: Add apple,t8112-aic compatible
  dt-bindings: arm: cpus: Add apple,avalanche & blizzard compatibles
  dt-bindings: watchdog: apple,wdt: Add t8112-wdt compatible
  dt-bindings: arm: apple: apple,pmgr: Add t8112-pmgr compatible
  dt-bindings: power: apple,pmgr-pwrstate: Add t8112 compatible

Link: https://lore.kernel.org/r/7263df01-aebc-2db5-f074-4805e0ae9fbc@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-14 15:19:26 +02:00
Bartosz Golaszewski
daa9e76d17 dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
Add the compatible for the Qualcomm Graphics Clock control module present
on sa8775p platforms. It matches the generic QCom GPUCC description. Add
device-specific DT bindings defines as well.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230411125910.401075-2-brgl@bgdev.pl
2023-04-13 20:36:09 -07:00
Srinivasa Rao Mandadapu
5c3a7dcce1 dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
When this property is set, the remoteproc is used to boot the
LPASS and therefore qdsp6ss clocks would be used to bring LPASS
out of reset, hence they are directly controlled by the remoteproc.

This is a cleanup done to handle overlap of regmap of lpasscc
and adsp remoteproc blocks.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407092255.119690-2-quic_mohs@quicinc.com
2023-04-13 20:17:12 -07:00