The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values from OCOTP. Document optional phandle to OCOTP nvmem
provider.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
DTSes with new i.MX 8M SoCs introduce their own compatibles so add them
to fix dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: tmu@30260000:
compatible:0: 'fsl,imx8mn-tmu' is not one of ['fsl,imx8mm-tmu', 'fsl,imx8mp-tmu']
From schema: Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: tmu@30260000:
compatible: ['fsl,imx8mn-tmu', 'fsl,imx8mm-tmu'] is too long
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: tmu@30260000:
compatible: Additional items are not allowed ('fsl,imx8mm-tmu' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>