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Author SHA1 Message Date
Arnd Bergmann
1422eb8585 Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 
Samsung DTS ARM64 changes for v6.9

Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding
support for:

1. Multi Core Timer (MCT) clocksource.
2. Several clock controllers (DTS and DT bindings) and use new clocks in
   several other device nodes.
3. More serial-interface instances: USI8 and USI12 with I2C.

Exynos850:
1. SPI and DMA controllers (PL330).

* tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: fsd: Add fifosize for UART in Device Tree
  arm64: dts: exynos: gs101: minor whitespace cleanup
  arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
  arm64: dts: exynos: gs101: define USI12 with I2C configuration
  arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
  dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
  arm64: dts: exynos: Add SPI nodes for Exynos850
  arm64: dts: exynos: Add PDMA node for Exynos850
  arm64: dts: exynos: gs101: use correct clocks for usi_uart
  arm64: dts: exynos: gs101: use correct clocks for usi8
  arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
  arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
  arm64: dts: exynos: gs101: define USI8 with I2C configuration
  arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
  arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
  arm64: dts: exynos: gs101: remove reg-io-width from serial
  arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
  dt-bindings: clock: exynos850: Add PDMA clocks
  dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit

Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2024-02-29 16:10:36 +01:00
Krzysztof Kozlowski
d5d1968345 arm64: dts: exynos: gs101: minor whitespace cleanup 
The DTS code coding style expects exactly one space before '{' and
around '=' characters.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240208105243.128875-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-02-12 14:21:28 +01:00
André Draszik
f9555ac036 arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole 
This bus has three USB-related devices attached to it:
    0x25: Maxim 77759 Type-C port controller
    0x35: Maxim 20339EWB Surge protection IC
    0x36: Maxim 77759 Fuel gauge
    0x57: NXP PCA9468 Battery charger
    0x66: Maxim 77759 PMIC
    0x69: Maxim 77759 Charger
where the Maxim 77759 has multiple i2c slave addresses.

These don't have (upstream) Linux drivers yet, but nevertheless we can
enable the bus so as to allow working on them (and to make i2cdetect /
i2cdump / etc. work).

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-8-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-02-08 09:06:40 +01:00
André Draszik
118261df42 arm64: dts: exynos: gs101: define USI12 with I2C configuration 
On the gs101-oriole board, i2c bus 12 has various USB-related
controllers attached to it.

Note the selection of the USI protocol is intentionally left for the
board dts file.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-7-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-02-08 09:06:04 +01:00
André Draszik
7d66d98b5b arm64: dts: exynos: gs101: enable cmu-peric1 clock controller 
Enable the cmu-peric1 clock controller. It feeds additional USI, I3C
and PWM interfaces / busses.

Note that &sysreg_peric1 needs a clock to be able to access its
registers and now that Linux knows about this clock, we need to add it
in this commit as well so as to keep &sysreg_peric1 working, so that
the clock can be enabled as and when needed.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-6-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-02-08 08:40:44 +01:00
André Draszik
21e4e8807b arm64: dts: exynos: gs101: use correct clocks for usi_uart 
Wrong pclk clocks have been used in this usi_uart instance here. For
USI and UART, we need the ipclk and pclk, where pclk is the bus clock.
Without it, nothing can work.

It is unclear what exactly is using USI0_UART_CLK, but it is not
required for the IP to be operational at this stage, while pclk is.
This also brings the DT in line with the clock names expected by the
usi and uart drivers.

Fixes: d97b6c902a ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks")
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240130093812.1746512-5-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-02-01 11:19:05 +01:00
André Draszik
512b5a875c arm64: dts: exynos: gs101: use correct clocks for usi8 
Wrong pclk clocks have been used in this usi8 instance here. For USI
and I2C, we need the ipclk and pclk, where pclk is the bus clock.
Without it, nothing can work.

It is unclear what exactly is using USI8_USI_CLK, but it is not
required for the IP to be operational at this stage, while pclk is.
This also brings the DT in line with the clock names expected by the
usi and i2c drivers.

Fixes: 6d44d1a1fb ("arm64: dts: exynos: gs101: define USI8 with I2C configuration")
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240130093812.1746512-4-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-02-01 11:19:02 +01:00
André Draszik
ca487bc277 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock 
Without the clock running, we can not access its registers, and now
that we have it, we should add it here so that it gets enabled as
and when needed.

Update the DTSI accordingly.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240126115517.1751971-2-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-26 13:00:30 +01:00
Tudor Ambarus
f655376913 arm64: dts: exynos: gs101: enable eeprom on gs101-oriole 
Enable the eeprom found on the battery connector.

The selection of the USI protocol is done in the board dts file because
the USI CONFIG register comes with a 0x0 reset value, meaning that USI8
does not have a default protocol (I2C, SPI, UART) at reset.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-9-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-23 13:53:20 +01:00
Tudor Ambarus
6d44d1a1fb arm64: dts: exynos: gs101: define USI8 with I2C configuration 
USI8 I2C is used to communicate with an eeprom found on the battery
connector. Define USI8 in I2C configuration.

USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
selection of the protocol is intentionally left for the board dts file.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-8-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-23 13:53:19 +01:00
Tudor Ambarus
d97b6c902a arm64: dts: exynos: gs101: update USI UART to use peric0 clocks 
Get rid of the dummy clock and start using the cmu_peric0 clocks
for the usi_uart and serial_0 nodes.

Tested the serial at 115200, 1000000 and 3000000 baudrates,
everthing went fine.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-7-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-23 13:53:19 +01:00
Tudor Ambarus
e62c706f3a arm64: dts: exynos: gs101: enable cmu-peric0 clock controller 
Enable the cmu-peric0 clock controller. It feeds USI and I3c.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-6-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-23 13:53:19 +01:00
Tudor Ambarus
af5c317a93 arm64: dts: exynos: gs101: remove reg-io-width from serial 
Remove the reg-io-width property in order to comply with the bindings.

The entire bus (PERIC) on which the GS101 serial resides only allows
32-bit register accesses. The reg-io-width dt property is disallowed
for the "google,gs101-uart" compatible and instead the iotype is
inferred from the compatible.

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-5-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-23 13:53:18 +01:00
Peter Griffin
927b46b543 arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node 
MCT has one global timer and 8 CPU local timers. The global timer
can generate 4 interrupts, and each local timer can generate an
interrupt making 12 interrupts in total.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20231222165355.1462740-4-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-23 13:53:18 +01:00
Tudor Ambarus
80c86ff680 arm64: dts: exynos: gs101: comply with the new cmu_misc clock names 
The cmu_misc clock-names were renamed to just "bus" and "sss" because
naming is local to the module, so cmu_misc is implied. As the bindings
and the device tree have not made a release yet, comply with the
renamed clocks.

Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240109114908.3623645-3-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-01-22 11:39:42 +01:00
Peter Griffin
6a5713fc78 arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support 
Add initial board support for the Pixel 6 phone code named Oriole. This
has been tested with a minimal busybox initramfs and boots to a shell.

Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20231211162331.435900-16-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-12-13 20:15:03 +01:00
Peter Griffin
ea89fdf24f arm64: dts: exynos: google: Add initial Google gs101 SoC support 
Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6
(oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
phones.

It features:
* 4xA55 Little cluster
* 2xA76 Mid cluster
* 2xX1 Big cluster

This commit adds the basic device tree for gs101 (SoC).
Further platform support will be added over time.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-15-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-12-13 20:14:56 +01:00