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23 Commits

Author SHA1 Message Date
Krzysztof Kozlowski
7dd900ea0e arm64: dts: microchip: minor whitespace cleanup around '=' 
The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org
[claudiu.beznea: added link]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2023-07-29 17:05:24 +03:00
Michael Walle
d5e64404e7 arm64: dts: sparx5: rename pinctrl nodes 
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220420194600.3416282-1-michael@walle.cc
Link: https://lore.kernel.org/r/20220319204628.1759635-5-michael@walle.cc
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-05-17 14:16:13 +02:00
Robert Marko
a34ebb1754 arm64: dts: microchip: sparx5: correct CPU address-cells 
There is no reason for CPU node #address-cells to be set at 2, so lets
change them to 1 and update the reg property accordingly.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-05-17 14:13:31 +02:00
Robert Marko
70be83708c arm64: dts: microchip: sparx5: do not use PSCI on reference boards 
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that
is shipped does not implement it as well.

I have tried flashing the latest BSP 2022.12 U-boot which did not work.
After contacting Microchip, they confirmed that there is no ATF for the
SoC nor PSCI implementation which is unfortunate in 2023.

So, disable PSCI as otherwise kernel crashes as soon as it tries probing
PSCI with, and the crash is only visible if earlycon is used.

Since PSCI is not implemented, switch core bringup to use spin-tables
which are implemented in the vendor U-boot and actually work.

Tested on PCB134 with eMMC (VSC5640EV).

Fixes: 6694aee00a ("arm64: dts: sparx5: Add basic cpu support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20230221105039.316819-1-robert.marko@sartura.hr
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-05-17 14:13:31 +02:00
Krzysztof Kozlowski
f217d94fc6 arm64: dts: microchip: add missing cache properties 
As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:

  sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property

Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-05-17 14:12:03 +02:00
Krzysztof Kozlowski
d105729968 arm64: dts: microchip: use "okay" for status 
"okay" over "ok" is preferred for status property.

Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20230127101824.93684-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-01-28 11:15:36 +01:00
Krzysztof Kozlowski
e76d8a16d1 arm64: dts: microchip: drop 0x from unit address 
By coding style, unit address should not start with 0x.

Link: https://lore.kernel.org/r/20221210113343.63864-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-01-13 11:36:04 +01:00
Krzysztof Kozlowski
09f4933a4f arm64: dts: microchip: adjust whitespace around '=' 
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220526204110.831805-1-krzysztof.kozlowski@linaro.org
 2022-06-16 13:45:26 -07:00
Krzysztof Kozlowski
402eb8ec54 arm64: dts: microchip: align SPI NOR node name with dtschema 
The node names should be generic and SPI NOR dtschema expects "flash".

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org
 2022-04-26 12:38:17 +02:00
Horatiu Vultur
6015fb905d dts: sparx5: Enable ptp interrupt 
Add support for ptp interrupt. This interrupt is used when using 2-step
timestamping. For each timestamp that is added in a queue, an interrupt
is generated.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 2022-03-04 13:03:09 +00:00
Steen Hegelund
920c293af8 arm64: dts: sparx5: Add the Sparx5 switch frame DMA support 
This adds the interrupt for the Sparx5 Frame DMA.

If this configuration is present the Sparx5 SwitchDev driver will use the
Frame DMA feature, and if not it will use register based injection and
extraction for sending and receiving frames to the CPU.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 2021-08-20 14:28:55 +01:00
Steen Hegelund
d0f482bb06 arm64: dts: sparx5: Add the Sparx5 switch node 
This provides the configuration for the currently available evaluation
boards PCB134 and PCB135.

The series depends on the following series currently on its way
into the kernel:

- Sparx5 Reset Driver
  Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 2021-06-24 11:28:13 -07:00
Lars Povlsen
7e1f91cbfa arm64: dts: sparx5: Add SGPIO devices 
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com
 2020-12-10 11:55:31 +01:00
Lars Povlsen
5ef399aa5c arm64: dts: sparx5: Add reset support 
This adds reset support to the Sparx5 SoC DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com
 2020-12-10 11:50:43 +01:00
Lars Povlsen
5df5012805 arm64: dts: sparx5: Add spi-nand devices 
This patch add spi-nand DT nodes to the applicable Sparx5 boards.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
 2020-09-16 11:39:51 +02:00
Lars Povlsen
ba4d1c074f arm64: dts: sparx5: Add spi-nor support 
This add spi-nor device nodes to the Sparx5 reference boards.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com
 2020-09-16 11:38:20 +02:00
Lars Povlsen
08ee16e954 arm64: dts: sparx5: Add SPI controller and associated mmio-mux 
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the
mmio-mux that is required to select the right SPI interface for a
given SPI device.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
 2020-09-16 10:34:21 +02:00
Lars Povlsen
d14f6a1ae0 arm64: dts: sparx5: Add hwmon temperature sensor 
This adds a hwmon temperature node sensor to the Sparx5 SoC.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
 2020-09-16 09:36:01 +02:00
Lars Povlsen
45145406f3 arm64: dts: sparx5: Add Sparx5 eMMC support 
This adds eMMC support to the applicable Sparx5 board configuration
files.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com
 2020-09-16 09:29:08 +02:00
Lars Povlsen
623910f4b9 arm64: dts: sparx5: Add i2c devices, i2c muxes 
This patch adds i2c devices and muxes to the Sparx5 reference boards.

Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2020-07-28 11:13:49 +02:00
Lars Povlsen
e4e06a50b0 arm64: dts: sparx5: Add Sparx5 SoC DPLL clock 
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.

Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2020-07-28 11:13:48 +02:00
Lars Povlsen
14bc6703b3 arm64: dts: sparx5: Add pinctrl support 
This add pinctrl support to the Microchip Sparx5 SoC.

Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2020-07-22 22:28:40 +02:00
Lars Povlsen
6694aee00a arm64: dts: sparx5: Add basic cpu support 
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).

Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2020-07-22 22:28:38 +02:00