bybrooklyn/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-04-30 04:22:32 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,266,087 Commits 1 Branch 928 Tags
697f3342477170bdf8759157bdc19c0b7b3e9d14
Commit Graph

134 Commits

Author SHA1 Message Date
Krzysztof Kozlowski
0d3eb7ff1f arm64: dts: sm8450: correct DMIC2 and DMIC3 pin config node names 
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:19 -06:00
Krzysztof Kozlowski
aa87ad5575 arm64: dts: qcom: sm8450: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Only
boot tested on hardware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-4-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Konrad Dybcio
6e115b75b4 arm64: dts: qcom: sm8450: Add missing interconnects to serial 
The serial ports did not have their interconnect paths specified when
they were first introduced. Fix that.

Fixes: 5188049c9b ("arm64: dts: qcom: Add base SM8450 DTSI")
Fixes: f583741847 ("arm64: dts: qcom: sm8450: add uart20 node")
Reported-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Suggested-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240116-topic-8450serial-v1-1-b685e6a5ad78@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 18:47:46 -06:00
Konrad Dybcio
36fd56ab4d arm64: dts: qcom: sm8450: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-10-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Krishna Kurapati
6bf150aef2 arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets 
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2
phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or
pwr_event. In one case, the hs_phy_irq was incorrectly defined with the
latter's IRQ number. Since the DT must describe the hw whether or not
the driver uses these interrupts, fix and add the missing entries in order
to describe the HW completely and accurately.

Also modify order of interrupts in accordance to bindings update.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:42:02 -06:00
Krzysztof Kozlowski
39859a1206 arm64: dts: qcom: sm8450: drop unneeded assigned-clocks from codec macros 
The MCLK clocks of codec macros have fixed 19.2 MHz frequency and
assigning clock rates is redundant.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231213162856.188566-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-16 23:19:14 -06:00
Krzysztof Kozlowski
565f4d00cd arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes 
Pin configuration for Soundwire bus should be set in Soundwire
controller nodes, not in the associated macro codec node.  This
placement change should not have big impact in general, because macro
codec is a clock provider for Soundwire controller, thus its devices is
probed first.  However it will have impact for disabled Soundwire buses,
e.g. WSA2, because after this change the pins will be left in default
state.

We also follow similar approach in newer SoCs, like Qualcomm SM8650.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231213162856.188566-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-16 23:19:14 -06:00
Manivannan Sadhasivam
052c9a1f14 arm64: dts: qcom: Use "pcie" as the node name instead of "pci" 
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct
node name for the controller instances.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-15 23:19:35 -06:00
Dmitry Baryshkov
75390b69d5 arm64: dts: qcom: sm8450: switch UFS QMP PHY to new style of bindings 
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231205032552.1583336-10-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-15 23:13:11 -06:00
Konrad Dybcio
9810647a04 arm64: dts: qcom: sm8450: Add GPU nodes 
Add the required nodes to support the A730 GPU.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-2-2a437588e563@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-15 23:07:02 -06:00
Neil Armstrong
11fcb81373 arm64: dts: qcom: sm8450: fix soundwire controllers node name 
Fix the following dt bindings check:
arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: soundwire-controller@31f0000: $nodename:0: 'soundwire-controller@31f0000' does not match '^soundwire(@.*)?$'
        from schema $id: http://devicetree.org/schemas/soundwire/qcom,soundwire.yaml#

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8450-upstream-soundwire-bindings-fix-v1-1-41d4844a5a7d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:12:28 -08:00
Krzysztof Kozlowski
20e886590a arm64: dts: qcom: sm8450: correct TX Soundwire clock 
The TX Soundwire controller should take clock from TX macro codec, not
VA macro codec clock, otherwise the clock stays disabled.  This looks
like a copy-paste issue, because the SC8280xp code uses here correctly
clock from TX macro.  The VA macro clock is already consumed by TX macro
codec, thus it won't be disabled by this change.

Fixes: 14341e76db ("arm64: dts: qcom: sm8450: add Soundwire and LPASS")
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231129140537.161720-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-02 20:44:58 -08:00
Neil Armstrong
c2c9fa1362 arm64: dts: qcom: sm8450: add TRNG node 
The SM8450 SoC has a True Random Number Generator, add the node with
the correct compatible set.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20231003-topic-sm8550-rng-v4-5-255e4d0ba08e@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-10-15 19:34:39 -07:00
Neil Armstrong
e735eab705 Revert "arm64: dts: qcom: sm8450: Add PRNG" 
This reverts commit 76a6dd7bfc ("arm64: dts: qcom: sm8450: Add PRNG"),
since the RNG HW on the SM8450 SoC is in fact a True Random Number Generator,
a more appropriate compatible should be instead as reported at [1].

[1] https://lore.kernel.org/all/20230818161720.3644424-1-quic_omprsing@quicinc.com/

Suggested-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230828-topic-sm8550-rng-v3-1-7a0678ca7988@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-09-20 07:54:55 -07:00
Dmitry Baryshkov
a912733ccb arm64: dts: qcom: sm8450: switch PCIe QMP PHY to new style of bindings 
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes). As a part of this conversion also
change the "refgen" name to more correct "rchng".

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-18-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-09-19 19:20:56 -07:00
Luca Weiss
018c949b32 arm64: dts: qcom: Use QCOM_SCM_VMID defines for qcom,vmid 
Since we have those defines available in a header, let's use them
everywhere where qcom,vmid property is used.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230818-qcom-vmid-defines-v1-1-45b610c96b13@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-09-19 19:16:35 -07:00
Konrad Dybcio
6578747ae2 arm64: dts: qcom: sm8450: Add RPMh stats 
SM8450 also exposes RPMh stats, hook them up for low power state
monitoring.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-8450_stats-v1-1-f26ae3fdf2cf@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:01:12 -07:00
Konrad Dybcio
76a6dd7bfc arm64: dts: qcom: sm8450: Add PRNG 
Add the Qualcomm Pseudo-Random Number Generator.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-8450_prng-v1-3-01becceeb1ee@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:39:44 -07:00
Rohit Agarwal
8ed9de7968 arm64: dts: qcom: sm8450: Update the RPMHPD bindings entry 
Update the RPMHPD bindings entry as per the new generic bindings defined
in rpmhpd.h for SM8450 SoC.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1689840545-5094-4-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-21 20:00:47 -07:00
Dmitry Baryshkov
4e125191e6 arm64: dts: qcom: sm8450: provide MDSS cfg interconnect 
Add support for the MDSS cfg-cpu bus vote on the SM8450 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230712121145.1994830-9-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-13 21:30:12 -07:00
Krzysztof Kozlowski
934a3b4d5a arm64: dts: qcom: minor whitespace cleanup around '=' 
The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185051.43867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-09 21:39:52 -07:00
Luca Weiss
86b0aef435 arm64: dts: qcom: sm8450: Use standalone ICE node for UFS 
With the ICE driver now merged let's convert the ufs node to use the new
style.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20221209-dt-binding-ufs-v5-5-c9a58c0a53f5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-09 21:33:27 -07:00
Krzysztof Kozlowski
b02966f868 arm64: dts: qcom: sm8450: correct crypto unit address 
Crypto node unit address should match reg.

Fixes: b92b0d2f75 ("arm64: dts: qcom: sm8450: add crypto nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230616174955.1783652-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-09 21:26:40 -07:00
Linus Torvalds
6c1561fb90 Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 
Pull ARM SoC devicetree updates from Arnd Bergmann:
 "The biggest change this time is for the 32-bit devicetree files, which
  are all moved to a new location, using separate subdirectories for
  each SoC vendor, following the same scheme that is used on arm64, mips
  and riscv. This has been discussed for many years, but so far we never
  did this as there was a plan to move the files out of the kernel
  entirely, which has never happened.

  The impact of this will be that all external patches no longer apply,
  and anything depending on the location of the dtb files in the build
  directory will have to change. The installed files after 'make
  dtbs_install' keep the current location.

  There are six added SoCs here that are largely variants of previously
  added chips. Two other chips are added in a separate branch along with
  their device drivers.

   - The Samsung Exynos 4212 makes its return after the Samsung Galaxy
     Express phone is addded at last. The SoC support was originally
     added in 2012 but removed again in 2017 as it was unused at the
     time.

   - Amlogic C3 is a Cortex-A35 based smart IP camera chip

   - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
     the still common MSM8916 (Snapdragon 410) phone chip that has been
     supported for a long time.

   - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
     laptop chips, used in the Lenovo Flex 5G, which is added along with
     the reference board.

   - Qualcomm SDX75 is the latest generation modem chip that is used as
     a peripherial in phones but can also run a standalone Linux. Unlike
     the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.

   - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
     Xuantie C910 core, a step up from all previously added rv64 chips.

  All of the above come with reference board implementations, those
  included there are 39 new board files, but only five more 32-bit this
  time, probably a new low:

   - Marantec Maveo board based on dhcor imx6ull module

   - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip

   - Epson Moverio BT-200 AR glasses based on TI OMAP4

   - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM

   - ICnova ADB4006 board based on Allwinner A20

  On the 64-bit side, there are also fewer addded machines than we had
  in the recent releases:

   - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
     EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.

   - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234

   - Qualcomm gains support for 6 reference boards on various members of
     their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
     phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
     of the various reference platforms for their new chips.

   - Rockchips support for several newer boards: Indiedroid Nova
     (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
     NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
     Fastrhino R66S/R68S (rk3568)

   - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
     Verdin family with AM62 COM, carrier and dev boards

  Other changes to existing boards contain the usual minor improvements
  along with

   - continued updates to clean up dts files based on dtc warnings and
     binding checks, in particular cache properties and node names

   - support for devicetree overlays on at91, bcm283x

   - significant additions to existing SoC support on mediatek,
     qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
     STM32MP1

  As usual, a lot more detail is available in the individual merge
  commits"

* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
  ARM: mvebu: fix unit address on armada-390-db flash
  ARM: dts: Move .dts files to vendor sub-directories
  kbuild: Support flat DTBs install
  ARM: dts: Add .dts files missing from the build
  ARM: dts: allwinner: Use quoted #include
  ARM: dts: lan966x: kontron-d10: add PHY interrupts
  ARM: dts: lan966x: kontron-d10: fix SPI CS
  ARM: dts: lan966x: kontron-d10: fix board reset
  ARM: dts: at91: Enable device-tree overlay support for AT91 boards
  arm: dts: Enable device-tree overlay support for AT91 boards
  arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
  ARM: dts: at91: use generic name for shutdown controller
  ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
  dt-bindings: firmware: brcm,kona-smc: convert to YAML
  riscv: dts: sort makefile entries by directory
  riscv: defconfig: enable T-HEAD SoC
  MAINTAINERS: add entry for T-HEAD RISC-V SoC
  riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
  riscv: dts: add initial T-HEAD TH1520 SoC device tree
  riscv: Add the T-HEAD SoC family Kconfig option
  ...
 2023-06-29 15:07:06 -07:00
Abel Vesa
b5b0649d5b arm64: dts: qcom: sm8450: Add missing interconnect paths to USB HC 
The USB HC node is missing the interconnect paths, so add them.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230602062016.1883171-6-abel.vesa@linaro.org
 2023-06-13 16:09:56 -07:00
Neil Armstrong
b92b0d2f75 arm64: dts: qcom: sm8450: add crypto nodes 
Add crypto engine (CE) and CE BAM related nodes and definitions
for the SM8450 SoC.

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[Bhupesh: Corrected the compatible list]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-12-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Konrad Dybcio
ec8bb9c5b1 arm64: dts: qcom: sm8450: Add missing RPMhPD OPP levels 
We need more granularity for things like the GPU. Add the missing levels.

This unfortunately requires some re-indexing, resulting in an ugly diff.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516005306.952821-1-konrad.dybcio@linaro.org
 2023-05-24 21:50:46 -07:00
Taniya Das
3c678552b0 arm64: dts: qcom: sm8450: Add video clock controller 
Add device node for video clock controller on Qualcomm SM8450 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-4-quic_tdas@quicinc.com
 2023-05-24 21:50:44 -07:00
Neil Armstrong
e5167da381 arm64: dts: qcom: sm8450: add ports subnodes in usb1 qmpphy node 
Add the USB3+DP Combo QMP PHY port subnodes in the SM8450 SoC DTSI
to avoid duplication in the devices DTs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-2-6c43d293995f@linaro.org
 2023-05-23 05:37:53 -07:00
Krzysztof Kozlowski
9c6e72fb20 arm64: dts: qcom: add missing cache properties 
Add required cache-level and cache-unified properties to fix warnings
like:

  qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
  qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
 2023-05-17 19:21:26 -07:00
Krzysztof Kozlowski
f34fbb71ce arm64: dts: qcom: fix indentation 
Correct indentation to use only tabs.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-1-krzysztof.kozlowski@linaro.org
 2023-05-17 19:21:26 -07:00
Krzysztof Kozlowski
d1333bce9e arm64: dts: qcom: sm8450: remove superfluous "input-enable" 
Pin configuration property "input-enable" was used with the intention to
disable the output, but this is done by default by Linux drivers.  Since
patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not
input-enable") the property is not accepted anymore.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407175807.124394-10-krzysztof.kozlowski@linaro.org
 2023-04-07 11:50:34 -07:00
Manivannan Sadhasivam
6340b391e1 arm64: dts: qcom: Remove "iommus" property from PCIe nodes 
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map"
properties for the PCIe nodes. First one passes the SMR mask to the iommu
driver and the latter specifies the SID for each PCIe device.

But with "iommus" property, the PCIe controller will be added to the
iommu group along with the devices. This makes no sense because the
controller will not initiate any DMA transaction on its own. And moreover,
it is not strictly required to pass the SMR mask to the iommu driver. If
the "iommus" property is not present, then the default mask of "0" would be
used which should work for all PCIe devices.

On the other side, if the SMR mask specified doesn't match the one expected
by the hypervisor, then all the PCIe transactions will end up triggering
"Unidentified Stream Fault" by the SMMU.

So to get rid of these hassles and also prohibit PCIe controllers from
adding to the iommu group, let's remove the "iommus" property from PCIe
nodes.

Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
 2023-04-06 11:32:54 -07:00
Krzysztof Kozlowski
d6573b4c20 arm64: dts: qcom: sm8450: simplify interrupts-extended 
The parent controller for both interrupts is GIC, so no need for
interrupts-extended.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-5-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Krzysztof Kozlowski
add214009d arm64: dts: qcom: sm8450: label the Soundwire nodes 
Use labels, instead of comments, for Soundwire controllers.  Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-2-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Neil Armstrong
35fa9a7fc5 arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes 
Fixes the following DT bindings check error:
domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org
 2023-04-04 20:22:08 -07:00
Bjorn Andersson
1554413537 Merge branch 'arm64-fixes-for-6.3' into arm64-for-6.4 
Merge the arm64-fixes-for-6.3 branch to avoid merge conflicts with
changes for v6.4.
 2023-03-28 15:32:04 -07:00
Neil Armstrong
e57430d248 arm64: dts: qcom: sm8450: fix pcie1 gpios properties name 
Add the final "s" to the pgio properties and fix the invalid "enable"
name to the correct "wake", checked against the HDK8450 schematics.

Fixes: bc6588bc25 ("arm64: dts: qcom: sm8450: add PCIe1 root device")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-4-0ca1bea1a843@linaro.org
 2023-03-24 10:45:51 -07:00
Neil Armstrong
c98a56395e arm64: dts: qcom: sm8450: remove invalid power-domain-names in pcie nodes 
Fixes the following DT bindings check error:
pci@1c00000: Unevaluated properties are not allowed ('power-domain-names' were unexpected)

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-3-0ca1bea1a843@linaro.org
 2023-03-24 10:45:51 -07:00
Neil Armstrong
bdd2f4ce5e arm64: dts: qcom: sm8450: add dp controller 
Add the Display Port controller subnode to the MDSS node.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-5-d78313cbc41d@linaro.org
 2023-03-23 07:36:46 -07:00
Neil Armstrong
d3054cec1e arm64: dts: qcom: sm8450: switch to usb3/dp combo phy 
The QMP PHY is a USB3/DP combo phy, switch to the newly
documented bindings and register the clocks to the GCC
and DISPCC controllers.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-4-d78313cbc41d@linaro.org
 2023-03-23 07:36:46 -07:00
Krzysztof Kozlowski
e18b829549 arm64: dts: qcom: drop redundant line breaks 
Remove trailing, redundant line breaks.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org
 2023-03-21 20:32:53 -07:00
Neil Armstrong
f28d912671 arm64: dts: qcom: sm8450: add port subnodes in dwc3 node 
Add ports subnodes in dwc3 node to avoid repeating the
same description in each board DT.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-7-552f3b721f9e@linaro.org
 2023-03-21 19:36:00 -07:00
Manivannan Sadhasivam
f57903c8f4 arm64: dts: qcom: sm8450: Fix the PCI I/O port range 
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.

While at it, let's use the missing 0x prefix for the addresses.

Fixes: bc6588bc25 ("arm64: dts: qcom: sm8450: add PCIe1 root device")
Fixes: 7b09b1b473 ("arm64: dts: qcom: sm8450: add PCIe0 RC device")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-13-manivannan.sadhasivam@linaro.org
 2023-03-15 17:24:35 -07:00
Manivannan Sadhasivam
413c8ecd48 arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Mukesh Ojha
d39469f5ce arm64: dts: qcom: sm8450: Add IMEM and PIL info region 
Add a simple-mfd representing IMEM on SM8450 and define the PIL
relocation info region, so that post mortem tools will be able
to locate the loaded remoteprocs.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1677079845-17650-1-git-send-email-quic_mojha@quicinc.com
 2023-03-14 19:30:48 -07:00
Manivannan Sadhasivam
8ba961d433 arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent 
The UFS controller on SM8450 supports cache coherency, hence add the
"dma-coherent" property to mark it as such.

Fixes: 07fa917a33 ("arm64: dts: qcom: sm8450: add ufs nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307153201.180626-2-manivannan.sadhasivam@linaro.org
 2023-03-09 13:10:53 -08:00
Krzysztof Kozlowski
6df6fab932 arm64: dts: qcom: sm8450: correct WSA2 assigned clocks 
The WSA2 assigned-clocks were copied from WSA, but the WSA2 uses its
own.

Fixes: 14341e76db ("arm64: dts: qcom: sm8450: add Soundwire and LPASS")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308123129.232642-1-krzysztof.kozlowski@linaro.org
 2023-03-09 12:13:41 -08:00
Krzysztof Kozlowski
60d2da2c91 arm64: dts: qcom: sm8450: drop incorrect cells from serial 
The serial/UART device node does not have children with unit addresses,
so address/size cells are not correct.

Fixes: f583741847 ("arm64: dts: qcom: sm8450: add uart20 node")
Fixes: 5188049c9b ("arm64: dts: qcom: Add base SM8450 DTSI")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230124084951.38195-3-krzysztof.kozlowski@linaro.org
 2023-02-08 15:57:19 -08:00
Konrad Dybcio
cce9c1d0b0 arm64: dts: qcom: sm8450: Fix DSIn PHY compatible 
Use the correct compatible so that the driver can probe properly.

Fixes: a6dd1206e4 ("arm64: dts: qcom: sm8450: add display hardware devices")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230123200552.553181-1-konrad.dybcio@linaro.org
 2023-02-08 15:57:19 -08:00