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164 Commits

Author SHA1 Message Date
Dmitry Baryshkov
c630cf8f3a clk: qcom: drop the SC7180 Modem subsystem clock driver 
This driver has never been used in the DT files merged to the kernel.
According to Sibi, it only worked on the pre-production devices. For the
production devices this functionality has been moved to the firmware.

Drop the driver to remove possible confusion.

Cc: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240216-drop-sc7180-mss-v1-1-0a8dc8d71c0c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 11:17:16 -06:00
Rajendra Nayak
76126a5129 clk: qcom: Add camcc clock driver for x1e80100 
Add the camcc clock driver for x1e80100

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-10-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 11:13:19 -06:00
Abel Vesa
06aff11619 clk: qcom: Add TCSR clock driver for x1e80100 
The TCSR clock controller found on X1E80100 provides refclks
for PCIE, USB and UFS. Add clock driver for it.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-9-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 11:13:19 -06:00
Rajendra Nayak
acddef6e17 clk: qcom: Add GPU clock driver for x1e80100 
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-8-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 11:13:19 -06:00
Rajendra Nayak
ee3f073903 clk: qcom: Add dispcc clock driver for x1e80100 
Add the dispcc clock driver for x1e80100.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-7-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 11:13:19 -06:00
Rajendra Nayak
161b7c401f clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 
Add support for the global clock controller found on X1E80100
based devices.

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20231205061002.30759-3-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 20:20:00 -08:00
Imran Shaik
e146252ac1 clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 
Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231123064735.2979802-4-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:47:05 -08:00
Neil Armstrong
8676fd4f38 clk: qcom: add the SM8650 GPU Clock Controller driver 
Add Graphics Clock Controller (GPUCC) support for SM8650 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-10-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:11:29 -08:00
Neil Armstrong
9e939f0083 clk: qcom: add the SM8650 Display Clock Controller driver 
Add Display Clock Controller (DISPCC) support for SM8650 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-9-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:11:29 -08:00
Neil Armstrong
e3388328e4 clk: qcom: add the SM8650 TCSR Clock Controller driver 
Add TCSR Clock Controller support for SM8650 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-8-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:11:29 -08:00
Neil Armstrong
aa381a2bdf clk: qcom: add the SM8650 Global Clock Controller driver, part 2 
Add Global Clock Controller (GCC) driver plumbing for the SM8650 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-7-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:11:29 -08:00
Bryan O'Donoghue
ff93872a9c clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC 
Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage
with additional CCI and IFE blocks and more granular clock parentage.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20231026105345.3376-4-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-12-07 08:02:33 -08:00
Bjorn Andersson
2643f0b069 Merge branch '20230909123431.1725728-1-quic_ajipan@quicinc.com' into clk-for-6.7 
Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse
of the defines from the DeviceTree binding in the DeviceTree source.
 2023-09-20 09:01:29 -07:00
Ajit Pandey
c32c4ef98b clk: qcom: Add GCC driver support for SM4450 
Add Global Clock Controller (GCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230909123431.1725728-5-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-09-20 09:01:20 -07:00
Jagadeesh Kona
ccc4e6a061 clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550 
Add support for the camera clock controller for camera clients to be
able to request for camcc clocks on SM8550 platform.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230707035744.22245-4-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-09-19 11:38:16 -07:00
Sricharan Ramabadhran
e3fdbef1ba clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 
Add support for the global clock controller found on IPQ5018
based devices.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:50:38 -07:00
Dmitry Baryshkov
bac4675a4d clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 
The two LCC drivers, msm8960 and mdm9615 are almost the same. The only
difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615
uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-6-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:25:16 -07:00
Srinivas Kandagatla
a5c9c3ba24 clk: qcom: Add lpass clock controller driver for SC8280XP 
Add support for the lpass clock controller found on SC8280XP based devices.
This would allow lpass peripheral loader drivers to control the clocks and
bring the subsystems out of reset.

Currently this patch only supports resets as the Q6DSP is in control of
LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg
channel.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230608125315.11454-4-srinivas.kandagatla@linaro.org
 2023-06-13 11:14:04 -07:00
Jagadeesh Kona
bfae40744b clk: qcom: gpucc-sm8550: Add support for graphics clock controller 
Add support for gpucc driver on SM8550, which provides clocks for the
graphics subsystem.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-3-quic_jkona@quicinc.com
 2023-05-26 18:24:05 -07:00
Konrad Dybcio
728692d49e clk: qcom: Add support for SM8450 GPUCC 
The GPUCC manages the clocks for the Adreno GPU found on the
sm8450 SoCs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-4-4f40e282af1d@linaro.org
 2023-05-26 18:23:24 -07:00
Imran Shaik
108cdc09b2 clk: qcom: Add GCC driver support for SDX75 
Add Global Clock Controller (GCC) support for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-6-quic_tdas@quicinc.com
 2023-05-24 21:47:17 -07:00
Jagadeesh Kona
f53153a379 clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550 
Add support for the video clock controller for video clients to be able
to request for videocc clocks on SM8550 platform.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-4-quic_jkona@quicinc.com
 2023-05-24 21:47:16 -07:00
Taniya Das
441fe711be clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450 
Add support for the video clock controller driver for peripheral clock
clients to be able to request for video cc clocks.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-3-quic_tdas@quicinc.com
 2023-05-24 21:47:16 -07:00
Konrad Dybcio
fd0b5b106f clk: qcom: Introduce SM8350 VIDEOCC 
Add support for the Video Clock Controller found on the SM8350 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-2-86c714a66a81@linaro.org
 2023-05-24 21:47:16 -07:00
Shazad Hussain
0afa16afc3 clk: qcom: add the GPUCC driver for sa8775p 
Add the clock driver for the Qualcomm Graphics Clock control module.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
[Bartosz: make ready for upstream]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230411125910.401075-3-brgl@bgdev.pl
 2023-04-13 20:36:09 -07:00
Devi Priya
d75b82cff4 clk: qcom: Add Global Clock Controller driver for IPQ9574 
Add Global Clock Controller (GCC) driver for ipq9574 based devices

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com
 2023-04-07 10:28:15 -07:00
Otto Pflüger
33cc27a47d clk: qcom: Add global clock controller driver for MSM8917 
This driver provides clocks, resets and power domains needed for various
components of the MSM8917 SoC and the very similar QM215 SoC.

According to [1] in the downstream kernel, the GPU clock has a different
source mapping on QM215 (gcc_gfx3d_map vs gcc_gfx3d_map_qm215).

[1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.6.2-28000-89xx.0/include/dt-bindings/clock/msm-clocks-hwio-8952.h#L298

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230223180935.60546-3-otto.pflueger@abscue.de
 2023-03-15 17:20:06 -07:00
Kathiravan T
3d89d52970 clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC 
Add support for the global clock controller found on IPQ5332 SoC. PLL
used on IPQ5332 is of type Stromer Plus PLL, however the programming
sequence is same as Stromer PLL, so lets re-use the Stromer PLL ops.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307062232.4889-5-quic_kathirav@quicinc.com
 2023-03-15 16:22:15 -07:00
Danila Tikhonov
a808d58ddf clk: qcom: Add Global Clock Controller (GCC) driver for SM7150 
Add support for the global clock controller found on SM7150
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.

Co-developed-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230213165318.127160-3-danila@jiaxyga.com
 2023-03-13 16:51:45 -07:00
Konrad Dybcio
092209f199 clk: qcom: Add GPU clock controller driver for SM6115 
Add support for the GPU clock controller found on SM6115.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-11-konrad.dybcio@linaro.org
 2023-03-13 12:59:44 -07:00
Konrad Dybcio
8397e24278 clk: qcom: Add GPU clock controller driver for SM6375 
Add support for the GPU clock controller found on SM6375.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-9-konrad.dybcio@linaro.org
 2023-03-13 12:59:44 -07:00
Konrad Dybcio
a6b1828681 clk: qcom: Add GPU clock controller driver for SM6125 
Add support for the GPU clock controller found on SM6125.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-7-konrad.dybcio@linaro.org
 2023-03-13 12:59:44 -07:00
Dmitry Baryshkov
ca574a5de5 clk: qcom: add msm8996 Core Bus Framework (CBF) support 
Add CBF clock driver as a part of MSM8996 CPU clocks. Significantly
based on AngeloGioacchino del Regno's work at [1].

The CBF is an interconnect between two CPU clusters, setting it up
properly is required for booting the MSM8996 with all four cores
enabled.

[1] https://github.com/sonyxperiadev/kernel/blob/aosp/LE.UM.2.3.2.r1.4/drivers/clk/qcom/clk-cpu-8996.c

Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[bjorn: Dropped partially uninitialized variable "ret" from cbf_clk_notifier_cb()]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120061417.2623751-4-dmitry.baryshkov@linaro.org
 2023-02-08 16:12:29 -08:00
Dmitry Baryshkov
0277263659 clk: qcom: add the driver for the MSM8996 APCS clocks 
Add a simple driver handling the APCS clocks on MSM8996. For now it
supports just a single aux clock, linking GPLL0 to CPU and CBF clocks.

Note, there is little sense in registering sys_apcs_aux as a child of
gpll0. The PLL is always-on. And listing the gpll0 as a property of the
apcs would delay its probing until the GCC has been probed (while we
would like for the apcs to be probed as early as possible).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Fixed spelling of register, per Stephen's feedback]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230126230319.3977109-8-dmitry.baryshkov@linaro.org
 2023-02-08 14:31:52 -08:00
Taniya Das
1c9efb0bc0 clk: qcom: Add QDU1000 and QRU1000 GCC support 
Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[bjorn: Made gcc_pcie_0_pipe_clk_src use clk_regmap_phy_mux_ops]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230112204446.30236-3-quic_molvera@quicinc.com
 2023-01-18 20:47:08 -06:00
Shazad Hussain
08c51ceb12 clk: qcom: add the GCC driver for sa8775p 
Add support for the Global Clock Controller found in the QTI SA8775P
platforms.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
[Bartosz: made the driver ready for upstream]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Moved to core_initcall(), per request of Konrad]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117180429.305266-3-brgl@bgdev.pl
 2023-01-18 16:23:00 -06:00
Neil Armstrong
90114ca114 clk: qcom: add SM8550 DISPCC driver 
Add support for the display clock controller found in SM8550
based devices.

This clock controller feeds the Multimedia Display SubSystem (MDSS).
This driver is based on the SM8450 support.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-3-8a03d348c572@linaro.org
 2023-01-10 12:19:19 -06:00
Abel Vesa
e9a7b78b20 clk: qcom: Add TCSR clock driver for SM8550 
The TCSR clock controller found on SM8550 provides refclks
for PCIE, USB and UFS. Add clock driver for it.

This patch is based on initial code downstream.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104093450.3150578-5-abel.vesa@linaro.org
 2023-01-06 11:10:37 -06:00
Konrad Dybcio
80f5451d9a clk: qcom: Add camera clock controller driver for SM6350 
Add support for the camera clock controller found on SM6350.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213152617.296426-2-konrad.dybcio@linaro.org
 2022-12-28 12:32:51 -06:00
Abel Vesa
955f2ea3b9 clk: qcom: Add GCC driver for SM8550 
Add Global Clock controller (GCC) driver for SM8550 SoC,
which includes the gcc resets and gdsc.

This patch is based on an initial downstream driver.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130112852.2977816-6-abel.vesa@linaro.org
 2022-12-01 17:28:31 -06:00
Konrad Dybcio
aec5f36cf6 clk: qcom: Add display clock controller driver for SM6375 
Add support for the display clock controller found on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115155808.10899-2-konrad.dybcio@linaro.org
 2022-11-15 10:46:36 -06:00
Bjorn Andersson
4a66e76fdb clk: qcom: Add SC8280XP display clock controller 
The Qualcomm SC8280XP platform has two display clock controller
instances, add support for these. Duplication between the two
implementations is reduced by reusing any constant data between the two
sets of clock data.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926203800.16771-3-quic_bjorande@quicinc.com
 2022-11-09 21:18:11 -06:00
Konrad Dybcio
184fdd873d clk: qcom: Add global clock controller driver for SM6375 
Add support for the global clock controller found on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921001303.56151-3-konrad.dybcio@somainline.org
 2022-09-27 22:25:57 -05:00
Bjorn Andersson
e55d937d8c clk: qcom: Add SC8280XP GPU clock controller 
Add driver for the GPU clock controller in the Qualcomm SC8280XP
platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[bjorn: Included kernel.h and lower-cased hex numbers]
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com
 2022-09-27 12:07:30 -05:00
Dmitry Baryshkov
16fb89f92e clk: qcom: Add support for Display Clock Controller on SM8450 
Add support for the dispcc on Qualcomm SM8450 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-4-dmitry.baryshkov@linaro.org
 2022-09-26 22:17:14 -05:00
Adam Skladowski
9b51878863 clk: qcom: Add display clock controller driver for SM6115 
Add support for the display clock controller found in SM6115/SM4250
based devices. This clock controller feeds the Multimedia Display
SubSystem (MDSS).
This driver is based upon one submitted for QCM2290.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220911164635.182973-3-a39.skl@gmail.com
 2022-09-26 22:17:13 -05:00
Stephan Gerhold
bf37a05744 clk: qcom: Add driver for MSM8909 GCC 
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks,
resets and power domains for the various hardware blocks in the SoC.
Add a driver for it to make it possible to enable additional
functionality for the SoC.

Work on this driver was originally started independently by Dominik,
I picked it up and added missing clocks/resets, as well as various
cleanup to bring it into shape for mainline.

Co-developed-by: Dominik Kobinski <dominikkobinski314@gmail.com>
Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com>
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-3-stephan.gerhold@kernkonzept.com
 2022-09-13 22:07:25 -05:00
Robert Foss
160758b05a clk: qcom: add support for SM8350 GPUCC 
The GPUCC manages the clocks for the Adreno GPU found on the
sm8350 SoCs.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org
 2022-07-06 15:20:59 -05:00
Vladimir Zapolskiy
6082037fe6 clk: qcom: add camera clock controller driver for SM8450 SoC 
Add  camera clock controller driver found on Qualcomm SM8450 SoC.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org
 2022-07-06 15:20:59 -05:00
Dmitry Baryshkov
74e4190cde clk: qcom: regmap: add PHY clock source implementation 
On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.

Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. Supplement the regmap-mux with
the new clk_regmap_phy_mux type, which implements such multiplexers
as a simple gate clocks.

This is possible since each of these multiplexers has just two clock
sources: one coming from the PHY and a reference (XO) one.  If the clock
is running off the from-PHY source, report it as enabled. Report it as
disabled otherwise (if it uses reference source).

This way the PHY will disable the pipe clock before turning off the
GDSC, which in turn would lead to disabling corresponding pipe_clk_src
(and thus it being parked to a safe, reference clock source). And vice
versa, after enabling the GDSC the PHY will enable the pipe clock, which
would cause pipe_clk_src to be switched from a safe source to the
working one.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org
 2022-06-25 21:36:07 -05:00