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19 Commits

Author SHA1 Message Date
Konrad Dybcio
d09ec6f987 clk: qcom: Use qcom_branch_set_clk_en() 
Instead of magically poking at the bit0 of branch clocks' CBCR, use
the newly introduced helper.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240212-topic-clk_branch_en-v7-2-5b79eb7278b2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 11:59:07 -06:00
Satya Priya Kakitapalli
429726494d clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco const 
The clk_init_data and pll_vco structures are never modified, make
them const.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240201-dispcc-sm8150-v1-1-cbeb89015e5d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-07 12:14:48 -06:00
Dmitry Baryshkov
c334ecf355 clk: qcom: dispcc-*: switch to module_platform_driver 
There is no need to register display clock controllers during subsys init
calls. Use module_platform_driver() instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-2-db799bd2feeb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-07 12:14:47 -06:00
Dmitry Baryshkov
009d43686e clk: qcom: dispcc-sm8250: switch to devm_pm_runtime_enable 
Switch to using the devm_pm_runtime_enable() instead of hand-coding
corresponding action to call pm_runtime_disable().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103145515.1164020-19-dmitry.baryshkov@linaro.org
 2023-01-10 22:05:08 -06:00
Robert Foss
f05dbd1a50 clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150 
SM8150 does not have any of the link_div_clk_src clocks, so
let's disable them for this SoC.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-6-robert.foss@linaro.org
 2022-11-05 23:38:19 -05:00
Robert Foss
8305ff41c7 clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350 
SM8350 supports embedded displayport, but the clocks for this
were previously not accounted for.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-5-robert.foss@linaro.org
 2022-11-05 23:38:19 -05:00
Robert Foss
e1a297a681 clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdsc 
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag,
so it should be enabled here.

This feature enables registers to maintain their state after
dis/re-enabling the GDSC.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-3-robert.foss@linaro.org
 2022-11-05 23:38:19 -05:00
Robert Foss
b5f84650fb clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350 
SM8350 does not have the EDP_GTC clock, so let's disable it
for this SoC.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-2-robert.foss@linaro.org
 2022-11-05 23:38:18 -05:00
Abel Vesa
b1ec8b53c9 clk: qcom: Drop mmcx gdsc supply for dispcc and videocc 
Both dispcc and videocc use mmcx power domain now.
Lets drop the supply mmcx from every gdsc.

Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 266e5cf39a ("arm64: dts: qcom: sm8250: remove mmcx regulator")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220713143200.3686765-1-abel.vesa@linaro.org
 2022-07-18 16:35:03 -05:00
Jonathan Marek
205737fe33 clk: qcom: add support for SM8350 DISPCC 
Add support to the SM8350 display clock controller by extending the SM8250
display clock controller, which is almost identical but has some minor
differences.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-5-robert.foss@linaro.org
 2022-07-06 15:20:59 -05:00
Taniya Das
6e6fec3f96 clk: qcom: dispcc: Update the transition delay for MDSS GDSC 
On SC7180 we observe black screens because the gdsc is being
enabled/disabled very rapidly and the GDSC FSM state does not work as
expected. This is due to the fact that the GDSC reset value is being
updated from SW.

The recommended transition delay for mdss core gdsc updated for
SC7180/SC7280/SM8250.

Fixes: dd3d066221 ("clk: qcom: Add display clock controller driver for SC7180")
Fixes: 1a00c962f9 ("clk: qcom: Add display clock controller driver for SC7280")
Fixes: 80a18f4a85 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/20220223185606.3941-2-tdas@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: lowercase hex]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-02-24 16:22:11 -08:00
Dmitry Baryshkov
6158b94ec8 clk: qcom: dispcc-sm8250: use runtime PM for the clock controller 
On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Use runtime PM calls to make sure that required power domain is
powered on while we access clock controller's registers.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210829154757.784699-4-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-10-14 17:50:48 -07:00
Bjorn Andersson
17fef808ed clk: qcom: dispcc-sm8250: Add additional parent clocks for DP 
The clock controller has two additional clock source pairs, in order to
support more than a single DisplayPort PHY. List these, so it's possible
to describe them all.

Also drop the unnecessary freq_tbl for the link clock sources, to allow
these parents to be used.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721224610.3035258-1-bjorn.andersson@linaro.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-07-27 11:30:16 -07:00
Bjorn Andersson
2ebdd326d1 clk: qcom: dispcc-sm8250: Add EDP clocks 
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-06-02 00:35:29 -07:00
Bjorn Andersson
8ff48c82df clk: qcom: dispcc-sm8250: Add sc8180x support 
The display clock controller in SC8180x is reused from SM8150, so add
the necessary compatible and wire up the driver to enable this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-06-02 00:35:26 -07:00
Dmitry Baryshkov
634e438f4c clk: qcom: dispcc-sm8250: use parent_hws where possible 
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-19-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-04-07 17:22:53 -07:00
Dmitry Baryshkov
6fec0c87ad clk: qcom: dispcc-sm8250: drop unused enum entries 
Drop unused enum entries from the list of parent enums.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-3-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-04-07 17:22:51 -07:00
Dmitry Baryshkov
3105c7c91f clk: qcom: dispcc-sm8250: handle MMCX power domain 
On SM8250 MMCX power domain is required to access MMDS_GDSC registers.
This power domain is expressed as mmcx-supply regulator property. Use
this regulator as MDSS_GDSC supply.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201023131925.334864-6-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-11-14 13:11:44 -08:00
Jonathan Marek
80a18f4a85 clk: qcom: Add display clock controller driver for SM8150 and SM8250 
Add support for the display clock controller found on SM8150 and SM8250.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250)
Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 18:18:06 -07:00