Konrad Dybcio
d09ec6f987
clk: qcom: Use qcom_branch_set_clk_en()
...
Instead of magically poking at the bit0 of branch clocks' CBCR, use
the newly introduced helper.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org >
Reviewed-by: Johan Hovold <johan+linaro@kernel.org >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Link: https://lore.kernel.org/r/20240212-topic-clk_branch_en-v7-2-5b79eb7278b2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-02-14 11:59:07 -06:00
Konrad Dybcio
31f8f3c827
clk: qcom: gcc-sm8350: Set delay for Venus CLK resets
...
Some Venus resets may require more time when toggling. Describe that.
The value is known for SM8350, see [1].
[1] dfe241edf2konrad.dybcio@linaro.org >
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-10-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-02-07 12:14:47 -06:00
Dmitry Baryshkov
1a500e0bc9
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
...
On SM8350 platform the PCIe PIPE clocks require additional handling to
function correctly. They are to be switched to the tcxo source before
turning PCIe GDSCs off and should be switched to PHY PIPE source once
they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops,
which provide support for this dance.
Fixes: 44c20c9ed3dmitry.baryshkov@linaro.org >
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org
2023-04-13 20:35:53 -07:00
Krzysztof Kozlowski
e35b4b9e83
clk: gcc-sm8350: drop PLL test clock
...
There is no user of core_bi_pll_test_se test clock so drop it.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
Link: https://lore.kernel.org/r/20221228140917.118861-3-krzysztof.kozlowski@linaro.org
2023-01-10 22:43:01 -06:00
Vinod Koul
33aa94fd94
clk: qcom: gcc-sm8350: explicitly include clk-provider.h
...
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org >
Reviewed-by: Stephen Boyd <sboyd@kernel.org >
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Link: https://lore.kernel.org/r/20211215113803.620032-2-vkoul@kernel.org
2021-12-20 23:14:50 -06:00
Dmitry Baryshkov
886fd9a4b4
clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
...
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Link: https://lore.kernel.org/r/20210405224743.590029-34-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-04-07 17:25:53 -07:00
Dmitry Baryshkov
097a888842
clk: qcom: gcc-sm8350: use parent_hws where possible
...
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Link: https://lore.kernel.org/r/20210405224743.590029-25-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-04-07 17:22:54 -07:00
Vinod Koul
3fade948fb
clk: qcom: gcc-sm8350: add gdsc
...
Add the GDSC found in GCC for SM8350 SoC
Signed-off-by: Vinod Koul <vkoul@kernel.org >
Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-02-14 12:56:55 -08:00
Vivek Aknurwar
44c20c9ed3
clk: qcom: gcc: Add clock driver for SM8350
...
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org >
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org >
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul <vkoul@kernel.org >
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Link: https://lore.kernel.org/r/20210127070811.152690-6-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-02-08 10:03:57 -08:00
