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1123 Commits

Author SHA1 Message Date
Bhawanpreet Lakha
1296423bf2 drm/amd/display: define DC_LOGGER for logger 
Created a DC_LOGGER define. This is used to
pass the logger into the macros.

Anywhere we need to use the logger we need to define
DC_LOGGER

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:35:13 -05:00
Bhawanpreet Lakha
2f3fd67a8a drm/amd/display: Use MACROS instead of dm_logger 
Created MACROS for all log levels. Also Replaced
usage of dm_logger_write to the defined MACROS

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:35:06 -05:00
Vitaly Prosyak
44c6f2e59e drm/amd/display: Handle HDR use cases. 
Implementation of de-gamma, blnd-gamma, shaper and
3d lut's.
Removed memory allocations in transfer functions.
Refactor color module.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:34:58 -05:00
Eric Bernstein
aef5f5237b drm/amd/display: Fix DAL surface change test 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:34:52 -05:00
Dmytro Laktyushkin
f553e68102 drm/amd/display: add per pipe dppclk 
v2: Fix commit title

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:34:33 -05:00
Dmytro Laktyushkin
8ff15a8fcc drm/amd/display: Update DCN OPTC registers 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:34:27 -05:00
Eric Yang
ea7ea2a8ca drm/amd/display: fix missing az disable in reset backend 
Optimization in reset backend skips disable stream if it is
already done in dc_stream_set_dpms. However that path does
not disable az in order to prevent audio from toggling
between internal and external displays. This still need to
be done.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:33:34 -05:00
Hersen Wu
cf1df90f35 drm/amd/display: Check DCN PState ASSERT failure 
[Description] ASIC change debug register definition

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:33:22 -05:00
Yue Hin Lau
3d53f42479 drm/amd/display: update cur_clock correctly within set bandwidth 
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-05 15:33:16 -05:00
Vitaly Prosyak
792474b736 drm/amd/display: De PQ implementation 
Some refactoring and optimizations in color module.
Added de gamma 2.2 & 2.4, also re gamma 2.2.
Added interface for diagnostic for de gamma & de pq.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:20:17 -05:00
Charlene Liu
ed8462acaf drm/amd/display: add force_trigger even to static screen control 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:20:00 -05:00
Yongqiang Sun
cf8c19a305 drm/amd/display: Add primary tmz_c and meta tmz tmz_c. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:37 -05:00
Krunoslav Kovac
8f8372c7d1 drm/amd/display: Optimize regamma calculations 
There are several optimizations:
1) Use predefined SRGB, don't calculate. This is the most common case.
2) Precompute HW X points at boot since they're fixed in ColModule
3) Precompute PQ - it never changes and is very CPU intensive in fixed pt.
4) Reduce number of points in ColModule to 512 (32x16) from 1024. This also
requires reducing some regions for legacy DCEs to 16 pts at most.

Performance
1) is super-fast, build_output_tf is 1-2us, down from 25000-30000.
Programming also fast since only one reg write.
2)+3) gives build_output_tf for PQ in ~100us range, down from ~80000-110000
2) + 4) results in slightly over 50% improvement. It gives an idea of the
savings when we can't use SRGB or PQ table (e.g. sdr white level > 80).

There's also a bit of refactoring: renaming some stuff that was misleading
and removing a lot of magic numbers that novices might not be able to
understand where they come from and what they mean.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:35 -05:00
Charlene Liu
c5fc7f59a7 drm/amd/display: resume from S3 bypass power down HW block. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:35 -05:00
Nikola Cornij
5f353208c3 drm/amd/display: Remove couple of unused OPTC registers 
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:31 -05:00
Eric Yang
5af9d013ef drm/amd/display: turn off cursor when disconnect plane 
As a precaution to prevent cases where cursor is enabled on a pipe
that is disabled, always turn off cursor when disconnecting plane.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:31 -05:00
Eric Bernstein
b3a1cbc0c5 drm/amd/display: Expose is_rgb_cspace function in hw_sequencer 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:30 -05:00
Eric Yang
33fd17d912 drm/amd/display: fix cursor related Pstate hang 
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK

If graphics plane go from 1 pipe to hsplit, the cursor updates
after mpc programming and unlock. Which means there is a window
of time where cursor is enabled on the wrong pipe if it's on
the right side of the screen (i.e. case where cursor need to
move from pipe 0 to pipe 3 post split). This will cause pstate hang.

Solution is to program the cursor while still locked.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:28 -05:00
Yongqiang Sun
f9549850a4 drm/amd/display: Null check for gamma correction. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:27 -05:00
Yongqiang Sun
24a30505f3 drm/amd/display: Check hubp in pipe_ctx not in res_pool. 
When disable plane, check power gate flag in hubp with pipe_ctx,
not with res_pool.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:27 -05:00
John Barberiz
3e5df76ae5 drm/amd/display: Bypass gamma set if not standard type 
If non-standard gamma type detected set identity matrix flag
so that we can bypass the gamma mode.

Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:25 -05:00
Charlene Liu
41b497421a drm/amd/display: eDP sequence BL off first then DP blank. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:41 -05:00
Charlene Liu
7c357e61e2 drm/amd/display: dpms off mute az audio endpoint only. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:39 -05:00
Arun Pandey
af1b00cdc6 drm/amd/display: Define dpp1_set_cursor_position in header 
Signed-off-by: Arun Pandey <Arun.Pandey@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:37 -05:00
Yongqiang Sun
3be1406a72 drm/amd/display: Add timing generator count to resource pool. 
Use tg count in resource pool for further reference.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:36 -05:00
Duke Du
3aa0caddf6 drm/amd/display: Update the register GRPH_SWAP_CNTL if surface pixel format changed. 
Signed-off-by: Duke Du <Duke.Du@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:33 -05:00
Hawking Zhang
407e75170f drm/amd/dc: include new ip and ip_offset headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:14 -05:00
Eric Bernstein
529c690ba8 drm/amd/display: Update dcn10_init_hw for FPGA 
Update dcn10_init_hw such that initialization of relevant
HW blocks for Maximus FPGA are also initialized (and not skipped).

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:37 -05:00
Yongqiang Sun
365acbaf46 drm/amd/display: Refactor remove mpcc processing. 
No need to use loop find opp, use opp in stream_res.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:35 -05:00
Yongqiang Sun
be2f449a19 drm/amd/display: Move opp reg access from hwss to opp module. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:34 -05:00
Yongqiang Sun
f8e413bf3c drm/amd/display: Move dpp reg access from hwss to dpp module. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:33 -05:00
Yongqiang Sun
2e9d6a571c drm/amd/display: Check opplist in pipe ctx not in res pool. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:32 -05:00
Andrew Jiang
405c50a07d drm/amd/display: Fix check for setting input TF 
We no longer change the plane state pointer for full updates, and as
such, we weren't setting the input transfer function and programming the
degamma registers when we are supposed to. Check for a full update, an
input TF change, or a gamma change in the update flags instead to correct
this.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:31 -05:00
Yongqiang Sun
e07f541f50 drm/amd/display: Use real BE and FE index to program regs. 
In case of some pipes are fused, pipe_idx should not
be used to program pipe regs. Instead of that, BE and FE
inst number should be used for reg index.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:29 -05:00
Yongqiang Sun
c8242b9858 drm/amd/display: Move hubp reg access from hwss to hubp module. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:28 -05:00
Krunoslav Kovac
146a9f6368 drm/amd/display: Pass full 3x4 remap matrix for color transform 
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:22 -05:00
Mikita Lipski
03736f4cf8 drm/amd/display: Prevent master programming in multisync 
Verify that the stream is master - and program only the slave displays

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:21 -05:00
Yongqiang Sun
8d6a741bf6 drm/amd/display: Use pipe_control_lock instead of tg lock. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:20 -05:00
Ken Chalmers
6d5d346f04 drm/amd/display: Eliminate several Maximus-specific code paths 
This allows Maximus emulation to more closely mirror actual silicon
execution.

* Enable pool->base.display_clock creation on Maximus.
* Enable rest of dce110_apply_ctx_to_hw on Maximus.
* Remove apply_ctx_to_hw_fpga (no longer necessary with the full
  dce110_apply_ctx_to_hw enabled).
* Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock
  for Maximus (this was the only fix-up necessary after enabling
  dce110_apply_ctx_to_hw; everything else works unmodified on
  Maximus).

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:18 -05:00
Yue Hin Lau
c24011d56b drm/amd/display: Expose dpp1_set_cursor_attributes 
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:54 -05:00
Eric Bernstein
72d520d4fa drm/amd/display: Update FMT and OPPBUF functions 
Updates to FMT and OPPBUF programming from HW team
pseudocode review.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:47 -05:00
Leo (Sunpeng) Li
e7899002cf drm/amd/display: Fix unused variable warnings. 
... since linux kernel compile treats warnings as errors.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:28 -05:00
Yue Hin Lau
b51adc77e2 drm/amd/display: Only blank DCN when we have set_blank implementation 
Also rename timing_generator to optc

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:22 -05:00
Eric Bernstein
39f26499c6 drm/amd/display: Put dcn_mi_registers with other structs 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:15 -05:00
Yue Hin Lau
4b8240bf91 drm/amd/display: hubp refactor 
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:08 -05:00
Yue Hin Lau
4b4f8f74a8 drm/amd/display: integrating optc pseudocode 
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:48:02 -05:00
Eric Bernstein
e9be38b42a drm/amd/display: Clean up DCN cursor code 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:47:50 -05:00
Eric Yang
f8668c099e drm/amd/display: reprogram surface config on scaling change 
When plane size changes, we need to reprogram surface pitch in addition
to viewport and scaler. This change is a conservative way to make this happen.
However it could be more optimized to move pitch programming into
mem_program_viewport.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Andrew Jiang <Andrew.Jiang@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:47:36 -05:00
Eric Bernstein
36192e7e57 drm/amd/display: Update HUBP 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:47:04 -05:00
Vitaly Prosyak
38cb3e96e0 drm/amd/display: Declare and share color space types for dcn's 
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-20 14:46:25 -05:00