2 Commits

Author	SHA1	Message	Date
Wesley Chalmers	39a1355fef	drm/amd/display: Add interface for ADD & DROP PIXEL Registers ... [WHY] HW has handed down a new sequence that requires access to these registers. v2: squash in DCN3.1 fixes (Alex) Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2021-06-08 12:22:42 -04:00
Bhawanpreet Lakha	2a3a0d5d79	drm/amd/display: Add DCN3 DCCG ... Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2020-07-01 01:59:14 -04:00