Commit Graph

14 Commits

Author SHA1 Message Date
Hugo Hu
bf79515610 drm/amd/display: reprogram det size while seamless boot
[Why]
During system boot in second screen only mode on a seamless boot system,
there is a chance that the pipe's det size might not be reset.

[How]
Reset the det size while resetting the pipe during seamless boot.

Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-26 18:41:21 -04:00
Charlene Liu
d755ce6465 drm/amd/display: correct z8_watermark 16bit to 20bit mask
remove double adjustment for DPREFCLK SS. dprefclk adjusted with SS is
used for dp audio only. if adjust DP_DTO, need to adjust VID_M/N

Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30 15:37:47 -04:00
Muhammad Ahmed
97c2eba5d6 drm/amd/display: disable clock gating logic reversed bug fix
[Why]
disable clock gating logic reversed bug fix

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-15 18:08:27 -04:00
Dmytro Laktyushkin
9ba90d760e drm/amd/display: add pixel rate based CRB allocation support
This feature is meant to unblock PSTATE for certain high end display
configs on dcn315. This is achieved by allocating CRB to detile buffer
based on display requirements to meet pstate latency hiding needs.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24 18:36:45 -04:00
Charlene Liu
dbc2309cac drm/amd/display: add hubbub_init related
Required by display init, also update get_dig_mode

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-13 14:59:48 -05:00
Charlene Liu
0c41021cb8 drm/amd/display: Expose few dchubbub functions
[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19 15:14:18 -04:00
Nicholas Kazlauskas
3107e1a7ae drm/amd/display: Fix p-state allow debug index on dcn31
[Why]
It changed since dcn30 but the hubbub31 constructor hasn't been
modified to reflect this.

[How]
Update the value in the constructor to 0x6 so we're checking the right
bits for p-state allow.

It worked before by accident, but can falsely assert 0 depending on HW
state transitions. The most frequent of which appears to be when
all pipes turn off during IGT tests.

Cc: Harry Wentland <harry.wentland@amd.com>

Fixes: e7031d8258 ("drm/amd/display: Add pstate verification and recovery for DCN31")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-25 12:40:24 -04:00
Nicholas Kazlauskas
e7031d8258 drm/amd/display: Add pstate verification and recovery for DCN31
[Why]
To debug when p-state is being blocked and avoid PMFW hangs when
it does occur.

[How]
Re-use the DCN10 hardware sequencer by adding a new interface for
verifying p-state high on the hubbub. The interface is mostly the
same as the DCN10 interface, but the bit definitions have changed for
the debug bus.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15 14:33:57 -04:00
Dmytro Laktyushkin
ca7f9d0aba drm/amd/display: fix yellow carp wm clamping
Fix clamping to match register field size

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-07 18:03:49 -05:00
Eric Yang
bbf8705079 drm/amd/display: refactor riommu invalidation wa
[Why]
A cleaner solution, only done once on boot.

[How]
Remove previous workaround and configure an extra
vmid one time on boot

Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-28 16:37:17 -04:00
Eric Yang
a4d5df1787 drm/amd/display: add workaround for riommu invalidation request hang
[Why]
When an riommu invalidation request come at the same time as a pipe is
disabled there can be a case where DCN cannot ACK the request if only
one VMID is setup in the inuse list.

[How]
Setup a second unused VMID will work around the issue.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23 10:07:58 -04:00
Dmytro Laktyushkin
dce7e5318d drm/amd/display: remove compbuf size wait
This tends to take miliseconds in certain scenarios and we'd rather not
wait that long. Due to how this interacts with det size update and
locking waiting should not be necessary as compbuf updates before
unlock.

Add a watch for config error instead as that is something we actually do
care about.

Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-21 13:39:25 -04:00
Josip Pavic
98e95e4f79 drm/amd/display: log additional register state for debug
[Why & How]
Extend existing state collection functions to add some additional
registers useful for debug, and add state collection function for DC
hubbub

Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-21 13:39:25 -04:00
Nicholas Kazlauskas
ba5a537181 drm/amd/display: Add DCN3.1 DCHHUB
Adds DCN3.1 DCHHUB programming and modifies DCN20/DCN30 shared
hardware sequencer helpers to use these hooks.

HW Blocks:

 +--------++------+       +----------+
 |DCHUBBUB|| HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                      ^
        v                      |
    +--------+             +--------+
    |  DPP   | <---------> |  DWB   |
    +--------+             +--------+
        |                      ^
        v                      |
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

No changes to MMHUBBUB or DWB programming, added to diagram for clarity.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:39:18 -04:00