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79 Commits

Author SHA1 Message Date
Wenjing Liu
17e8f215cd drm/amd/display: Update pipe resource interfaces for DCN35 
Pipe resource interfaces were changed.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:08 -04:00
Mustapha Ghaddar
a3e6f21403 drm/amd/display: Add DPIA Link Encoder Assignment Fix for DCN35 
For DPIA we should have preferred DIG assignment based on DPIA selected
as per the ASIC design

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:08 -04:00
Sung-huai Wang
ecbaaa544b drm/amd/display: fix static screen detection setting for DCN35 
set_static_screen_control has been updated for DCN3 series. Update it
for DCN35.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Sung-huai Wang <danny.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:08 -04:00
Charlene Liu
82f4ab32f5 drm/amd/display: Add z8_marks related in dml for DCN35 
Add z8 watermarks to struct for DCN35.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:07 -04:00
Duncan Ma
f1eb045639 drm/amd/display: Fix dig register undefined 
[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.

[How]
Fix stream encoder register define list.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:07 -04:00
Charlene Liu
e4b6d48d05 drm/amd/display: Temporarily disable clock gating 
Temporarily disable dchubbub clock gating, registers:
.DISPCLK_R_DCHUBBUB_GATE_DIS
.DCFCLK_R_DCHUBBUB_GATE_DIS

need to follow up with sequence issue.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Leo Chen <sanchuan.chen@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:07 -04:00
Muhammad Ahmed
f6340612d4 drm/amd/display: disable clock gating logic 
Disable clock gating logic.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:07 -04:00
Taimur Hassan
c056bf3746 drm/amd/display: Add reset for SYMCLKC_FE_SRC_SEL 
To prevent confusion after symclk has already been disabled.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-20 16:24:07 -04:00
Qingqing Zhuo
1a2ab18c8f drm/amd/display: Drop unused registers 
[Why & How]
Some registers are never used in the driver
but defined. Remove them.

Reviewed-by: Roman Li <roman.li@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-11 17:17:24 -04:00
Yang Li
9f720e4999 drm/amd/display: clean up some inconsistent indentings 
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_hwseq.c:159 dcn35_init_hw() warn: inconsistent indentig

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-06 14:33:10 -04:00
Yang Li
77dcb33ccb drm/amd/display: clean up one inconsistent indenting 
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_resource.c:1877 dcn35_resource_construct() warn: inconsistent indenting

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-06 14:33:08 -04:00
Yang Li
3b96ec9633 drm/amd/display: Remove duplicated include in dcn35_hwseq.c 
./drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c: clk_mgr.h is included more than once.

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-06 14:32:36 -04:00
Yang Li
bde5f439b8 drm/amd/display: Remove duplicated include in dcn35_optc.c 
./drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c: dcn35_optc.h is included more than once.

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-06 14:32:34 -04:00
Yang Li
209d15ffd0 drm/amd/display: Remove duplicated include in dcn35_resource.c 
./drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c: dcn31/dcn31_dio_link_encoder.h is included more than once.

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-09-06 14:32:31 -04:00
Srinivasan Shanmugam
eae3699175 drm/amd/display: Adjust kdoc for 'optc35_set_odm_combine' 
Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_optc.c:46: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Enable CRTC

Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Qingqing Zhuo
0fa45b6aea drm/amd/display: Add DCN35 Resource 
[Why & How]
Add resource handling for DCN35.

v2: drop unused guard
v3: drop dml2 dependencies for now (Alex)

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
ec129fa356 drm/amd/display: Add DCN35 init 
[Why & How]
Add init files for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
6f8b7565cc drm/amd/display: Add DCN35 HWSEQ 
[Why & How]
Add HWSEQ handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
327959a489 drm/amd/display: Add DCN35 DSC 
[Why & How]
Add DSC handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
c10ad60fda drm/amd/display: Add DCN35 MMHUBBUB 
[Why & How]
Add MMHUBBUB handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
4435fc4240 drm/amd/display: Add DCN35 HUBBUB 
[Why & How]
Add HUBBUB handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
74c06a327d drm/amd/display: Add DCN35 HUBP 
[Why & How]
Add HUBP handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:15 -04:00
Qingqing Zhuo
284246a1c3 drm/amd/display: Add DCN35 DWB 
[Why & How]
Add DWB handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00
Qingqing Zhuo
bd831267c6 drm/amd/display: Add DCN35 DPP 
[Why & How]
Add DPP handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00
Qingqing Zhuo
ffb8c23718 drm/amd/display: Add DCN35 OPP 
[Why & How]
Add OPP handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00
Qingqing Zhuo
b9c96af677 drm/amd/display: Add DCN35 OPTC 
[Why & How]
Add OPTC handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00
Qingqing Zhuo
920f879c83 drm/amd/display: Add DCN35 PG_CNTL 
[Why & How]
Add PG_CNTL handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00
Qingqing Zhuo
e0b394a87a drm/amd/display: Add DCN35 DIO 
[Why & How]
Add DIO handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00
Qingqing Zhuo
819af8dc9a drm/amd/display: Add DCN35 DCCG 
[Why & How]
Add DCCG handling for DCN35.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:14 -04:00