This updates the GPU headers to latest from mesa, using gen_header.py
(which is used to generate headers at bulid time for mesa), rather than
headergen2 (which doesn't have proper support for A6XX vs A7XX register
variants).
Mostly just uninteresting churn, but there are a couple spots in a7xx
paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are
a7xx specific.
Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/574880/
Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5
Small bit of .c churn in the phy code to adapt to split up of phy
related registers.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Update the gmu_pdc registers for A640 and A650.
Some of the RSCC registers on A650 are in a separate region.
Note this also changes the address of these registers:
RSCC_TCS1_DRV0_STATUS
RSCC_TCS2_DRV0_STATUS
RSCC_TCS3_DRV0_STATUS
Based on the values in msm-4.14 and msm-4.19 kernels.
v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Newer GPUs have different GMU firmware path.
v3: updated a6xx_gmu_fw_load based on feedback, including gmu_write_bulk,
and removed extra whitespace change
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
