Dmitry Baryshkov
8844f467d6
drm/msm/dpu: make error messages at dpu_core_irq_register_callback() more sensible
...
There is little point in using %ps to print a value known to be NULL. On
the other hand it makes sense to print the callback symbol in the
'invalid IRQ' message. Correct those two error messages to make more
sense.
Fixes: 6893199183dmitry.baryshkov@linaro.org >
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/585565/
Link: https://lore.kernel.org/r/20240330-dpu-irq-messages-v1-1-9ce782ae35f9@linaro.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
2024-04-01 16:02:40 -07:00
Dmitry Baryshkov
b19e6f7dd2
drm/msm/dpu: use devres-managed allocation for interrupts data
...
Use devm_kzalloc to create interrupts data structure. This allows us to
remove corresponding kfree and drop dpu_hw_intr_destroy() function.
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/570038/
Link: https://lore.kernel.org/r/20231201211845.1026967-4-dmitry.baryshkov@linaro.org
2023-12-05 22:14:33 +03:00
Dmitry Baryshkov
5a9d50150c
drm/msm/dpu: shift IRQ indices by 1
...
In order to simplify IRQ declarations, shift IRQ indices by 1. This
makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
to explicitly set the 'no interrupt' fields in catalog structures.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/550938/
Link: https://lore.kernel.org/r/20230802100426.4184892-9-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2023-10-09 12:17:41 +03:00
Dmitry Baryshkov
6be6ece920
drm/msm/dpu: stop using raw IRQ indices in the kernel traces
...
In preparation to reworking IRQ indcies, stop using raw indices in
kernel traces. Instead use a pair of register index and bit. This
corresponds closer to the values in HW catalog.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/550935/
Link: https://lore.kernel.org/r/20230802100426.4184892-8-dmitry.baryshkov@linaro.org
2023-10-09 00:34:44 +03:00
Dmitry Baryshkov
6893199183
drm/msm/dpu: stop using raw IRQ indices in the kernel output
...
In preparation to reworking IRQ indcies, stop using raw IRQ indices in
kernel output (both printk and debugfs). Instead use a pair of register
index and bit. This corresponds closer to the values in HW catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Patchwork: https://patchwork.freedesktop.org/patch/550933/
Link: https://lore.kernel.org/r/20230802100426.4184892-7-dmitry.baryshkov@linaro.org
2023-10-09 00:34:44 +03:00
Dmitry Baryshkov
56acb1b620
drm/msm/dpu: make the irq table size static
...
The size of the irq table is static, it has MDP_INTR_MAX * 32 interrupt
entries. Provide the fixed length and drop struct_size() statement.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/550927/
Link: https://lore.kernel.org/r/20230802100426.4184892-6-dmitry.baryshkov@linaro.org
2023-10-09 00:34:44 +03:00
Dmitry Baryshkov
ea4842ed62
drm/msm/dpu: add helper to get IRQ-related data
...
In preparation to reworking IRQ indices, move irq_tbl access to
a separate helper.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/550931/
Link: https://lore.kernel.org/r/20230802100426.4184892-5-dmitry.baryshkov@linaro.org
2023-10-09 00:34:44 +03:00
Dmitry Baryshkov
a652648336
drm/msm/dpu: extract dpu_core_irq_is_valid() helper
...
In preparation to reworking IRQ indices, move irq_idx validation to
a separate helper.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/550929/
Link: https://lore.kernel.org/r/20230802100426.4184892-4-dmitry.baryshkov@linaro.org
2023-10-09 00:34:44 +03:00
Dmitry Baryshkov
e75e45c25b
drm/msm/dpu: remove irq_idx argument from IRQ callbacks
...
There is no point in passing the IRQ index to IRQ callbacks, no function
uses that. Drop it at last.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/550925/
Link: https://lore.kernel.org/r/20230802100426.4184892-3-dmitry.baryshkov@linaro.org
2023-10-09 00:34:44 +03:00
Dmitry Baryshkov
bf8198cc3b
drm/msm/dpu: autodetect supported interrupts
...
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this with looping over the enabled INTF blocks
to setup the irq mask.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549654/
Link: https://lore.kernel.org/r/20230727144543.1483630-4-dmitry.baryshkov@linaro.org
2023-08-02 12:36:33 +03:00
Dmitry Baryshkov
370891f0d9
drm/msm/dpu: split interrupt address arrays
...
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org >
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Fixes: c731461322dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549653/
Link: https://lore.kernel.org/r/20230727144543.1483630-3-dmitry.baryshkov@linaro.org
2023-08-02 12:36:32 +03:00
Dmitry Baryshkov
c54b4c3519
drm/msm/dpu: inline __intr_offset
...
Inline __intr_offset(), there is no point in having a separate oneline
function for setting base block address.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org >
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549655/
Link: https://lore.kernel.org/r/20230727144543.1483630-2-dmitry.baryshkov@linaro.org
2023-08-02 12:36:32 +03:00
Marijn Suijten
ec6e9b673a
drm/msm/dpu: Describe TEAR interrupt registers for DSI interfaces
...
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block. Wire up the IRQ register
masks in the interrupt table for enabling, reading and clearing them.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/534244/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-18-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2023-05-22 10:14:18 +03:00
Marijn Suijten
f0408020bf
drm/msm/dpu: Take INTF index as parameter in interrupt register defines
...
Instead of hardcoding many register defines for every INTF and AD4 index
with a fixed stride, turn the defines into singular chunks of math that
compute the address using the base and this fixed stride multiplied by
the index given as argument to the definitions.
MDP_SSPP_TOP0_OFF is dropped as that constant is zero anyway, and all
register offsets related to it live in dpu_hwio.h.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/534221/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-11-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2023-05-22 10:14:17 +03:00
Marijn Suijten
85340c0256
drm/msm/dpu: Reindent REV_7xxx interrupt masks with tabs
...
Use tabs for consistency with the other interrupt register definitions,
rather than spaces.
Fixes: ed6154a13689688e21194a352c2fc1marijn.suijten@somainline.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/534212/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-4-27ce1a5ab5c6@somainline.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
2023-04-26 16:47:08 -07:00
Marijn Suijten
e9d9ce5462
drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header
...
These offsets do not fall under the MDP TOP block and do not fit the
comment right above. Move them to dpu_hw_interrupts.c next to the
repsective MDP_INTF_x_OFF interrupt block offsets.
Fixes: 25fdd5933emarijn.suijten@somainline.org >
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/534203/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-3-27ce1a5ab5c6@somainline.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
2023-04-26 16:46:57 -07:00
Bjorn Andersson
4a352c2fc1
drm/msm/dpu: Introduce SC8280XP
...
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/514398/
Link: https://lore.kernel.org/r/20221207220012.16529-3-quic_bjorande@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2023-01-12 21:45:17 +02:00
Marijn Suijten
d45e5744ab
drm/msm/dpu: Print interrupt index in addition to the mask
...
The mask only describes the `irq_idx % 32` part, making it generally
impossible to deduce what interrupt is being enabled/disabled. Since
`debug/core_irq` in debugfs (and other prints) also include the full
`DPU_IRQ_IDX()` value, print the same full value here for easier
correlation instead of only adding the `irq_idx / 32` part.
Furthermore, make the dbgstr messages more consistent.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org >
Reviewed-by: Martin Botka <martin.botka@somainline.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/512460/
Link: https://lore.kernel.org/r/20221121222456.437815-1-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2023-01-08 22:21:08 +02:00
Dmitry Baryshkov
9403f9a42c
drm/msm/dpu: merge base_off with blk_off in struct dpu_hw_blk_reg_map
...
There is little point in keeping a separate MDP address and block offset
in this struct. Merge them to form a new blk_addr field used for all
register access.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/488017/
Link: https://lore.kernel.org/r/20220601161349.1517667-4-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2022-07-06 08:43:54 -07:00
Dmitry Baryshkov
3208496720
drm/msm/dpu: constify struct dpu_mdss_cfg
...
Mark struct dpu_mdss_cfg instance as a const pointer. This is mostly a
preparation for the next patch.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/488164/
Link: https://lore.kernel.org/r/20220602202447.1755115-7-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-07-04 21:05:27 +03:00
Dmitry Baryshkov
129ae533fa
drm/msm/dpu: remove hwversion field from data structures
...
The driver should not depend on hw revision for detecting features.
Instead it should use features from the hw catalog. Drop the hwversion
field from struct dpu_mdss_cfg and struct dpu_hw_blk_reg_map.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/488160/
Link: https://lore.kernel.org/r/20220602202447.1755115-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-07-04 21:05:27 +03:00
Dmitry Baryshkov
dfba7f5b24
drm/msm/dpu: remove NULL-ness check in dpu_hw_intr_destroy
...
There is no need to check that kfree() argument is not NULL. Remove
extra check and call kfree() unconditionally.
Reported-by: kernel test robot <lkp@intel.com >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Link: https://lore.kernel.org/r/20220507114009.1696278-1-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2022-05-07 09:56:42 -07:00
Vinod Polimera
01013ba9bb
drm/msm/disp/dpu1: avoid clearing hw interrupts if hw_intr is null during drm uninit
...
If edp modeset init is failed due to panel being not ready and
probe defers during drm bind, avoid clearing irqs and dereference
hw_intr when hw_intr is null.
BUG: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
Call trace:
dpu_core_irq_uninstall+0x50/0xb0
dpu_irq_uninstall+0x18/0x24
msm_drm_uninit+0xd8/0x16c
msm_drm_bind+0x580/0x5fc
try_to_bring_up_master+0x168/0x1c0
__component_add+0xb4/0x178
component_add+0x1c/0x28
dp_display_probe+0x38c/0x400
platform_probe+0xb0/0xd0
really_probe+0xcc/0x2c8
__driver_probe_device+0xbc/0xe8
driver_probe_device+0x48/0xf0
__device_attach_driver+0xa0/0xc8
bus_for_each_drv+0x8c/0xd8
__device_attach+0xc4/0x150
device_initial_probe+0x1c/0x28
Changes in V2:
- Update commit message and coreect fixes tag.
Fixes: f25f656608quic_vpolimer@quicinc.com >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Stephen Boyd <swboyd@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/484430/
Link: https://lore.kernel.org/r/1651509846-4842-1-git-send-email-quic_vpolimer@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-05-07 02:10:34 +03:00
Marijn Suijten
4b8dd2be5c
drm/msm/dpu: Use indexed array initializer to prevent mismatches
...
While there's a comment pointing from dpu_intr_set to dpu_hw_intr_reg
and vice-versa, an array initializer using indices makes it so that the
indices between the enum and array cannot possibly get out of sync even
if they're accidentially ordered wrongly. It is still useful to keep
the comment to be made aware where the register offset mapping resides
while looking at dpu_hw_intr_reg.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/476358/
Link: https://lore.kernel.org/r/20220226194633.204501-1-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-05-02 02:39:35 +03:00
Dmitry Baryshkov
6ee11c415e
drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq
...
Get rid of dpu_encoder_helper_register_irq/unregister_irq helpers, call
dpu_core_register/unregister_callback directly, without surrounding them
with helpers.
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Reviewed-by: Stephen Boyd <swboyd@chromium.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/474698/
Link: https://lore.kernel.org/r/20220217043148.480898-5-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-05-02 02:07:07 +03:00
Dmitry Baryshkov
c929ac60b3
drm/msm/dpu: allow just single IRQ callback
...
DPU interrupts code allows multiple callbacks per interrut. In reality
none of the interrupts is shared between blocks (and will probably never
be). Drop support for registering multiple callbacks per interrupt to
simplify interrupt handling code.
Reported-by: kernel test robot <lkp@intel.com >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Stephen Boyd <swboyd@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/474701/
Link: https://lore.kernel.org/r/20220217043148.480898-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-05-02 02:07:07 +03:00
Dmitry Baryshkov
52db0f2b9f
drm/msm/dpu: remove always-true argument of dpu_core_irq_read()
...
The argument clear of the function dpu_core_irq_read() is always true.
Remove it.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Reviewed-by: Stephen Boyd <swboyd@chromium.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/474697/
Link: https://lore.kernel.org/r/20220217043148.480898-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-05-02 02:07:07 +03:00
Dmitry Baryshkov
dd77ce4da8
drm/msm/dpu: remove extra wrappers around dpu_core_irq
...
Remove extra dpu_irq_* wrappers from dpu_kms.c, merge them directly into
dpu_core_irq_* functions.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Reviewed-by: Stephen Boyd <swboyd@chromium.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/474696/
Link: https://lore.kernel.org/r/20220217043148.480898-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-05-02 02:07:07 +03:00
Bjorn Andersson
148e852f29
drm/msm/dpu: Add INTF_5 interrupts
...
SC8180x has the eDP controller wired up to INTF_5, so add the interrupt
register block for this interface to the list.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Link: https://lore.kernel.org/r/20220215043353.1256754-1-bjorn.andersson@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-02-18 20:15:11 +03:00
Vinod Koul
07567d596e
drm/msm/dpu: Update function parameter documentation
...
dpu_core_irq_callback_handler() function comments seem to have become
stale and emit a warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:147:
warning: Function parameter or member 'dpu_kms' not described in 'dpu_core_irq_callback_handler'
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:147:
warning: Excess function parameter 'arg' description in 'dpu_core_irq_callback_handler'
Fix by updating the documentation
Signed-off-by: Vinod Koul <vkoul@kernel.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Link: https://lore.kernel.org/r/20220210114106.290669-3-vkoul@kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-02-18 20:15:11 +03:00
Vinod Koul
651988cc2b
drm/msm/dpu: Update the comment style
...
The multi line comment style is wrongly used as kernel-doc comment. This
gives a warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:17:
warning: This comment starts with '/**', but isn't a kernel-doc comment.
Refer Documentation/doc-guide/kernel-doc.rst
Update the style to fix this.
Signed-off-by: Vinod Koul <vkoul@kernel.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Link: https://lore.kernel.org/r/20220210114106.290669-2-vkoul@kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-02-18 20:15:11 +03:00
Bjorn Andersson
89688e2119
drm/msm/dpu: Add more of the INTF interrupt regions
...
In addition to the other 7xxx INTF interrupt regions, SM8350 has
additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
these. The 7xxx naming scheme of the bits are kept for consistency.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Reviewed-by: Robert Foss <robert.foss@linaro.org >
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Link: https://lore.kernel.org/r/20211123154050.40984-1-bjorn.andersson@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-11-29 16:19:58 -08:00
Dmitry Baryshkov
f25f656608
drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr
...
As dpu_core_irq was merged into dpu_hw_intr, merge data structures too,
removing the need for a separate data structure.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210617222029.463045-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-10-15 12:59:19 -07:00
Dmitry Baryshkov
6087623e7c
drm/msm/dpu: don't clear IRQ register twice
...
We already clear the IRQ status register before processing IRQs, so do
not clear the register again. Especially do not clear the IRQ status
_after_ processing the IRQ as this way we can loose the event.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210617222029.463045-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-10-15 12:59:19 -07:00
Dmitry Baryshkov
a73033619e
drm/msm/dpu: squash dpu_core_irq into dpu_hw_interrupts
...
With dpu_core_irq being the wrapper around dpu_hw_interrupts, there is
little sense in having them separate. Squash them together to remove
another layer of abstraction (hw_intr ops).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210617222029.463045-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-10-15 12:59:19 -07:00
Bjorn Andersson
c96348a8fb
drm/msm/dpu: Avoid ABBA deadlock between IRQ modules
...
Handling of the interrupt callback lists is done in dpu_core_irq.c,
under the "cb_lock" spinlock. When these operations results in the need
for enableing or disabling the IRQ in the hardware the code jumps to
dpu_hw_interrupts.c, which protects its operations with "irq_lock"
spinlock.
When an interrupt fires, dpu_hw_intr_dispatch_irq() inspects the
hardware state while holding the "irq_lock" spinlock and jumps to
dpu_core_irq_callback_handler() to invoke the registered handlers, which
traverses the callback list under the "cb_lock" spinlock.
As such, in the event that these happens concurrently we'll end up with
a deadlock.
Prior to '1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")'
the enable/disable of the hardware interrupt was done outside the
"cb_lock" region, optimitically by using an atomic enable-counter for
each interrupt and an warning print if someone changed the list between
the atomic_read and the time the operation concluded.
Rather than re-introducing the large array of atomics, this change
embraces the fact that dpu_core_irq and dpu_hw_interrupts are deeply
entangled and make them share the single "irq_lock".
Following this step it's suggested that we squash the two parts into a
single irq handling thing.
Fixes: 1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Link: https://lore.kernel.org/r/20210611170003.3539059-1-bjorn.andersson@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-06-23 07:33:55 -07:00
Dmitry Baryshkov
18b20ac0ec
drm/msm/dpu: drop remains of old irq lookup subsystem
...
There is no more need for the dpu_intr_type types, dpu_irq_map table,
individual intr defines and obsolete_irq field. Drop all of them now.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210516202910.2141079-6-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-06-23 07:32:15 -07:00
Dmitry Baryshkov
667e9985ee
drm/msm/dpu: replace IRQ lookup with the data in hw catalog
...
The IRQ table in the dpu_hw_interrupts.h is big, ugly, and hard to
maintain. There are only few interrupts used from that table. Newer
generations use different IRQ locations. Move this data to hw catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210516202910.2141079-5-dmitry.baryshkov@linaro.org
[fixup tracepoint compile warns/err]
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-06-23 07:32:15 -07:00
Dmitry Baryshkov
98fbe6bb5b
drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock
...
Always call dpu_hw_intr_clear_intr_status_nolock() from the
dpu_hw_intr_dispatch_irqs(). This simplifies the callback function
(which call clears the interrupts anyway) and enforces clearing the hw
interrupt status.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210516202910.2141079-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-06-23 07:32:15 -07:00
Dmitry Baryshkov
09e3a2b442
drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs
...
There is little sense in reading interrupt statuses and right after that
going after the array of statuses to dispatch them. Merge both loops
into single function doing read and dispatch.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Link: https://lore.kernel.org/r/20210516202910.2141079-2-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-06-23 07:32:15 -07:00
Krishna Manikandan
dc8a4973fd
drm/msm/disp/dpu1: add flags to indicate obsolete irqs
...
Some irqs which are applicable for sdm845 target are no
longer applicable for sc7180 and sc7280 targets. Add a
flag to indicate the irqs which are obsolete for a
particular target so that these irqs are skipped while
checking for matching irq lookup index.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org >
Link: https://lore.kernel.org/r/1617688895-26275-4-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-04-07 11:05:48 -07:00
Krishna Manikandan
7e4526db30
drm/msm/disp/dpu1: add vsync and underrun irqs for INTF_5
...
INTF_5 is used by EDP panel in SC7280 target. Add vsync
and underrun irqs needed by INTF_5 to dpu irq map.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org >
Link: https://lore.kernel.org/r/1617688895-26275-3-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-04-07 11:05:48 -07:00
Krishna Manikandan
a8eca8a1a5
drm/msm/disp/dpu1: increase the range of interrupts in dpu_irq_map
...
Currently, each register in the dpu interrupt set is allowed
to have a maximum of 32 interrupts. With the introduction
of INTF_5_VSYNC and INTF_5_UNDERRUN irqs for EDP panel,
the total number of interrupts under INTR_STATUS register
in dpu_irq_map will exceed 32. Increase the range of each
interrupt register to 64 to handle this.
This patch has dependency on the below series:
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=461193
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org >
Link: https://lore.kernel.org/r/1617688895-26275-2-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-04-07 11:05:48 -07:00
Krishna Manikandan
ed6154a136
drm/msm/disp/dpu1: add intf offsets for SC7280 target
...
Interface block offsets are different for SC7280 family
when compared to existing targets. These offset values
are used to access the interface irq registers. This
change adds proper interface offsets for SC7280 target.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org >
Link: https://lore.kernel.org/r/1617685792-14376-3-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-04-07 11:05:48 -07:00
Lee Jones
849652c1ab
drm/msm/disp/dpu1/dpu_hw_interrupts: Demote kernel-doc formatting misuse
...
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:246: error: Cannot parse struct or union!
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:756: error: Cannot parse struct or union!
Cc: Rob Clark <robdclark@gmail.com >
Cc: Sean Paul <sean@poorly.run >
Cc: David Airlie <airlied@linux.ie >
Cc: Daniel Vetter <daniel@ffwll.ch >
Cc: Shubhashree Dhar <dhar@codeaurora.org >
Cc: linux-arm-msm@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: freedreno@lists.freedesktop.org
Signed-off-by: Lee Jones <lee.jones@linaro.org >
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2020-12-03 08:47:08 -08:00
Tian Tao
c731461322
drm/msm: Add missing struct identifier
...
fix warnings reported by make W=1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:195: warning: cannot
understand function prototype: 'const struct dpu_intr_reg
dpu_intr_set[] = '
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:252: warning: cannot
understand function prototype: 'const struct dpu_irq_type
dpu_irq_map[] = '
Signed-off-by: Tian Tao <tiantao6@hisilicon.com >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2020-11-04 08:26:25 -08:00
Shubhashree Dhar
0846cca394
msm: disp: dpu1: add support to access hw irqs regs depending on revision
...
Current code assumes that all the irqs registers offsets can be
accessed in all the hw revisions; this is not the case for some
targets that should not access some of the irq registers.
This change adds the support to selectively remove the irqs that
are not supported in some of the hw revisions.
Changes in v1:
- Add support to selectively remove the hw irqs that are not
not supported.
Changes in v2:
- Remove unrelated changes.
Changes in v3:
- Remove change-id (Stephen Boyd).
- Add colon in variable description to match kernel-doc (Stephen Boyd).
- Change macro-y way of variable description (Jordon Crouse).
- Remove unnecessary if checks (Jordon Crouse).
- Remove extra blank line (Jordon Crouse).
Changes in v4:
- Remove checkpatch errors.
Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2020-01-02 15:08:23 -08:00
Thomas Gleixner
97fb5e8d9b
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284
...
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 and
only version 2 as published by the free software foundation this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 294 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de >
Reviewed-by: Allison Randal <allison@lohutok.net >
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com >
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org >
2019-06-05 17:36:37 +02:00
Jayant Shekhar
5e1023d613
drm/msm/dpu: Clean up dpu hw interrupts
...
Remove unused functions and macros from files handling
dpu hardware interrupts.
changes in v2:
Removed clear_interrupt_status (Jordan Crouse)
changes in v3:
Changed commit text
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org >
Signed-off-by: Sean Paul <seanpaul@chromium.org >
2019-02-01 10:35:55 -05:00
Jeykumar Sankaran
25fdd5933e
drm/msm: Add SDM845 DPU support
...
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org >
Signed-off-by: Archit Taneja <architt@codeaurora.org >
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org >
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org >
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org >
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org >
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org >
Signed-off-by: Sean Paul <seanpaul@chromium.org >
[robclark minor rebase]
Signed-off-by: Rob Clark <robdclark@gmail.com >
2018-07-26 10:45:04 -04:00
