Jason Gunthorpe
bf9cd9fef9
iommu/tegra: Use tegra_dev_iommu_get_stream_id() in the remaining places
...
This API was defined to formalize the access to internal iommu details on
some Tegra SOCs, but a few callers got missed. Add them.
The helper already masks by 0xFFFF so remove this code from the callers.
Suggested-by: Thierry Reding <thierry.reding@gmail.com >
Reviewed-by: Thierry Reding <treding@nvidia.com >
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com >
Link: https://lore.kernel.org/r/7-v2-16e4def25ebb+820-iommu_fwspec_p1_jgg@nvidia.com
Signed-off-by: Joerg Roedel <jroedel@suse.de >
2023-12-12 10:18:51 +01:00
Ben Skeggs
4500031f86
drm/nouveau/ltc: split color vs depth/stencil zbc counts
...
These differ on Ampere.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com >
Reviewed-by: Lyude Paul <lyude@redhat.com >
2022-11-09 10:45:10 +10:00
Ben Skeggs
0afc1c4caa
drm/nouveau/ltc: switch to instanced constructor
...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com >
Reviewed-by: Lyude Paul <lyude@redhat.com >
2021-02-11 11:49:53 +10:00
Thierry Reding
0d0d498265
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation
...
There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.
Signed-off-by: Thierry Reding <treding@nvidia.com >
Signed-off-by: Ben Skeggs <bskeggs@redhat.com >
2020-01-15 10:49:59 +10:00
