The two commits referenced below break mono playback via I2S DAI because
they set BCLK to half the required speed. For PCM transport over I2S, the
number of transmitted channels is always 2, even for mono playback.
Fixes: dcd79364bf ("ASoC: codec: tlv3204: Enable 24 bit audio support")
Fixes: 40b3713628 ("ASoC: tlv320aic32x4: Fix bdiv clock rate derivation")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220810104156.665452-1-p.zabel@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Don't populate the array clocks on the stack but instead it
static. Makes the object code smaller by 316 bytes.
Before:
text data bss dec hex filename
63668 28264 0 91932 1671c ./sound/soc/codecs/tlv320aic32x4.o
After:
text data bss dec hex filename
62616 29000 0 91616 165e0 ./sound/soc/codecs/tlv320aic32x4.o
(gcc version 10.2.0)
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210801064807.138641-1-colin.king@canonical.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The TAS2505/TAS2521 does support only three processing block options, unlike
TLV320AIC32x4 which supports 25. This is documented in TI slau472 2.5.1.2
Processing Blocks and Page 0 / Register 60: DAC Instruction Set - 0x00 / 0x3C.
Limit the Processing Blocks maximum value to 3 on TAS2505/TAS2521 and select
processing block PRB_P1 always, because for the configuration of teh codec
implemented in this driver, this is the best quality option.
Fixes: b4525b6196 ("ASoC: tlv320aic32x4: add support for TAS2505")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Claudius Heine <ch@denx.de>
Cc: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210720200348.182139-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
The TAS2505/TAS2521 does support up to two channels, LEFT and RIGHT,
which are being alternated on the audio data bus by Word Clock, WCLK.
This is documented in TI slau472 2.7.1 Digital Audio Interface. Note
that both the LEFT and RIGHT channels are only used for audio INPUT,
while only the LEFT channel is used for audio OUTPUT.
Fixes: b4525b6196 ("ASoC: tlv320aic32x4: add support for TAS2505")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Claudius Heine <ch@denx.de>
Cc: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210708091229.56443-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
None of the TAS2505 outputs are stereo, do not pretend they are by
implementing them using SOC*DOUBLE* macros referencing the same
register twice, use SOC*SINGLE* instead. Fix volume ranges and mute
control for the codec according to datasheet.
Fixes: b4525b6196 ("ASoC: tlv320aic32x4: add support for TAS2505")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Claudius Heine <ch@denx.de>
Cc: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210708091255.56502-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
While this driver can already handle different device variants, the
variant information cannot be used in the driver code and therefor
cannot have different code paths depending on the device variant.
This change adds a `type` value into the `aic32x4_priv` structure, that
contains a device variant identifier, which was set when the driver was
bound to the device.
Signed-off-by: Claudius Heine <ch@denx.de>
Link: https://lore.kernel.org/r/20210617085230.1851503-2-ch@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
At power-up the analog circuits may take up to one full second before
being charged with the default configuration. Using the analog blocks
before they are ready generates a *very* crappy sound.
Enable the fast charge feature, which will require a bit more power
than normal charge but will definitely speed up the starting operation
by shrinking this delay to up to 40 ms.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20200911173140.29984-4-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
To avoid the actual PLL settings to differ from the state expected by
the clock driver, the codec should only be fully reset before the clocks
are registered. But we also need to ensure that the software reset
happens at all before clock registration, as not all boards have a reset
GPIO.
Move the software reset from aic32x4_component_probe() to
aic32x4_probe() and reorder the reset and registration sequence:
1. Reset via GPIO (if available)
2. Reset via software
3. Register component
4. Register clocks
Note that aic32x4_component_probe() is only called after aic32x4_probe()
has finished, so the reset in aic32x4_component_probe() was happening too
late.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20200902133043.19504-2-matthias.schiffer@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Moving GPIO reset to a later stage and before clock registration to
ensure that the host system and codec clocks are in sync. If the host
register clock values prior to gpio reset, the last configured codec clock
is registered to the host. The codec then gets gpio resetted setting the
codec clocks to their default value, causing a mismatch. Host system will
skip clock setting thinking the codec clocks are already at the requested
rate.
ADC reset is added to ensure the next audio capture does not have
undesired artifacts. It is probably related to the original code
where the probe function resets the ADC prior to 1st record.
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Reviewed-by: Sia Jee Heng <jee.heng.sia@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20200812094631.4698-4-michael.wei.hong.sit@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
snd_soc_dai_digital_mute() is internally using both
mute_stream() (1) or digital_mute() (2), but the difference between
these 2 are only handling direction.
We can merge digital_mute() into mute_stream
int snd_soc_dai_digital_mute(xxx, int direction)
{
...
else if (dai->driver->ops->mute_stream)
(1) return dai->driver->ops->mute_stream(xxx, direction);
else if (direction == SNDRV_PCM_STREAM_PLAYBACK &&
dai->driver->ops->digital_mute)
(2) return dai->driver->ops->digital_mute(xxx);
...
}
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Link: https://lore.kernel.org/r/874kqhxxhz.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details you
should have received a copy of the gnu general public license along
with this program if not write to the free software foundation inc
51 franklin street fifth floor boston ma 02110 1301 usa
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option [no]_[pad]_[ctrl] any later version this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not write to the free
software foundation inc 51 franklin street fifth floor boston ma
02110 1301 usa
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 176 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Fixes gcc '-Wunused-but-set-variable' warning:
sound/soc/codecs/tlv320aic32x4.c: In function 'aic32x4_setup_clocks':
sound/soc/codecs/tlv320aic32x4.c:669:16: warning: variable 'mclk_rate' set but not used [-Wunused-but-set-variable]
It is not used since introduction in
commit 96c3bb0023 ("ASoC: tlv320aic32x4: Dynamically Determine Clocking")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
PowerTune controls the power level of the chip. On playback this
indirectly controls things like the gain of the various output
amplifiers. This can allow for the decrease of output levels
from the codec. This adds controls for those power levels to
the driver.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add a switch for setting common mode voltage. This can allow
for higher drive levels on the amplifier outputs.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The common pins were mistakenly not added to the DAPM graph.
Adding these pins will allow valid graphs to be created.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The clocking and processing blocks are now properly set up to
support 192000 sample rates. Allow drivers to ask for that.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
mclk is not used by anything anymore. Remove support for it.
All that information now comes from the clock tree.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The sysclk is now managed by the CCF. Change this function
to merely find the system clock and set it using
clk_set_rate.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The existing code uses a static lookup table to determine the
settings of the various clock devices on board the chip. This is
limiting in a couple of ways. First, this doesn't allow for any
master clock rates other than the three that have been
precalculated. Additionally, new sample rates are difficult to
add to the table. Witness that the chip is capable of 192000 Hz
sampling, but it is not provided by this driver. Last, if the
driver is clocked by something that isn't a crystal, the
upstream clock may not be able to achieve exactly the rate
requested in the driver. This will mean that clocking will be
slightly off for the sampling clock or that it won't work at all.
This patch determines the settings for all of the clocks at
runtime considering the real conditions of the clocks in the
system. The rules for the clocks are in TI's SLAA557 application
guide on pages 37, 51 and 77.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Move these to separate helper functions. This looks cleaner and fits
better with the new clock setting in CCF.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Control the clock gating to the various clock components to use
the CCF. This allows us to prepare_enalbe only 3 clocks and the
relationships assigned to them will cause upstream clockss to
enable automatically. Additionally we can do this in a single
call to the CCF.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage BDIV divider as components in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage DAC/ADC dividers as components in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage codec clock input as a component in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage the on-board PLL as a component in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Different processing blocks are required for different sampling
rates and power parameters. Set the processing blocks based
on this information.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Break the clock setting logic out from the main hw_params. It's
rather large and unweildy and makes for a large function. This
also better enables some of the following changes to the clock
tree access in the driver.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
As stated in 'TLV320AIC3254 Application Reference Guide' ([1]):
3.2 Device Startup Lockout Times
After the TLV320AIC3254 initializes through hardware reset at power-up
or software reset, the internal registers initialize to default values.
This initialization takes place within 1ms after pulling the RESET
signal high. During this initialization phase, no register-read or
register-write operation should be performed on ADC or DAC coefficient
buffers. Also, no block within the codec should be powered up during
the initialization phase.
[1] http://www.ti.com/lit/an/slaa408a/slaa408a.pdf
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: Fixes for v5.0
Quite a big batch of fixes here. There's a couple of things going on,
the main one is that we found some issues with not deferring probe when
we should, causing us to skip some driver initialization. The fixes for
this then in turn exposed some issues with how we were searching for
components which had previously gone unnoticed due to the original
issue.
There's also been the normal driver specific stuff and there's been what
looks like several batches of automated scanning for issues which have
generated quite a large set of smaller fixes for potential crashes and
missed error handling.
SND_SOC_DAPM_MICBIAS is deprecated, replace it with SND_SOC_DAPM_SUPPLY.
MICBIAS voltage wasn't supplied to the microphone with the older
SND_SOC_DAPM_MICBIAS widget, hence the microphone wouldn't work.
This patch fixes the problem.
Signed-off-by: b-ak <anur.bhargav@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
During the bootup of the kernel, the DAPM bias level is in the OFF
state. As soon as the DAPM framework kicks in it pushes the codec
into STANDBY state.
The probe function doesn't prepare the clock, and STANDBY state
does a clk_disable_unprepare() without checking the previous state.
This leads to an OOPS.
Not transitioning from an OFF state to the STANDBY state fixes the
problem.
Signed-off-by: b-ak <anur.bhargav@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
