Commit Graph

3 Commits

Author SHA1 Message Date
Tinghan Shen
210b3ab932 ASoC: SOF: mediatek: Add mt8186 dsp clock support
Add adsp clock on/off support on mt8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Yaochun Hung <yc.hung@mediatek.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220422055659.8738-4-tinghan.shen@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-25 14:04:45 +01:00
Tinghan Shen
570c14dc92 ASoC: SOF: mediatek: Add mt8186 sof fw loader and dsp ops
Add mt8186-loader module with ops callback to load and run firmware
on mt8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Yaochun Hung <yc.hung@mediatek.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220422055659.8738-3-tinghan.shen@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-25 14:04:44 +01:00
Tinghan Shen
1f0214a86d ASoC: SOF: mediatek: Add mt8186 hardware support
Add support of SOF on Mediatek mt8186 SoC.
MT8186 has 2 Cortex A76 cores paired with 6 Cortex A55 cores.
It also has Cadence HiFi-5 DSP single core. The IPC communication
between AP and DSP is based on shared DRAM and mailbox interrupt.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Yaochun Hung <yc.hung@mediatek.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220422055659.8738-2-tinghan.shen@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-25 14:04:43 +01:00