3 Commits

Author	SHA1	Message	Date
Roger Quadros	b2bac25a4d	memory: omap-gpmc: Support WAIT pin edge interrupts ... OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered interrupts if not used for memory wait state insertion. Support these interrupts via the gpmc IRQ domain. The gpmc IRQ domain interrupt map is: 0 - NAND_fifoevent 1 - NAND_termcount 2 - GPMC_WAIT0 edge 3 - GPMC_WAIT1 edge, and so on Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>	2016-04-15 11:55:06 +03:00
Roger Quadros	d2d00862df	memory: omap-gpmc: Support general purpose input for WAITPINs ... OMAPs can have 2 to 4 WAITPINs that can be used as general purpose input if not used for memory wait state insertion. The first user will be the OMAP NAND chip to get the NAND read/busy status using gpiolib. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>	2016-04-15 11:54:12 +03:00
Roger Quadros	3c76f6119a	memory: omap-gpmc: Move device tree binding to correct location ... omap-gpmc.c is a memory controller so move the binding to the right place. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>	2016-04-15 11:54:03 +03:00