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662 Commits

Author SHA1 Message Date
Ben Skeggs
4691409b3e drm/nouveau/disp/sor/gm107: training pattern registers are like gm200 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
 2016-06-07 08:11:25 +10:00
Ben Skeggs
a8953c52b9 drm/nouveau/disp/sor/gf119: both links use the same training register 
It appears that, for whatever reason, both link A and B use the same
register to control the training pattern.  It's a little odd, as the
GPUs before this (Tesla/Fermi1) have per-link registers, as do newer
GPUs (Maxwell).

Fixes the third DP output on NVS 510 (GK107).

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
 2016-06-07 08:11:14 +10:00
Ben Skeggs
383d0a419f drm/nouveau/gr/gf100-: update sm error decoding from gk20a nvgpu headers 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
 2016-06-02 13:53:41 +10:00
Ben Skeggs
9057c8d750 drm/nouveau/ltc/gm107-: fix typo in the address of NV_PLTCG_LTC0_LTS0_INTR 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
 2016-06-02 13:53:38 +10:00
Ben Skeggs
bc9139d23f drm/nouveau/bios/disp: fix handling of "match any protocol" entries 
As it turns out, a value of 0xff means "any protocol" and not "VGA".

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
 2016-06-02 13:53:30 +10:00
Ben Skeggs
ca79e49d6a drm/nouveau/gr/gf100-: fix race condition in fecs/gpccs ucode 
This is a simplied version of the fix by Roy in fdo#93629.  While this
doesn't appear to fix the issues for the users in that report, it's a
real issue that deserves to be resolved.

Reported-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
f9e2029443 drm/nouveau/core: recognise GM108 chipsets 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
00f50c662c drm/nouveau/gr/gm107-: fix touching non-existent ppcs in attrib cb setup 
Also removes an XXX; according to nvgpu headers the field is called
NV_PGRAPH_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3, so, apparently not some
magic we need to figure out :)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
a00ecf2212 drm/nouveau/gr/gk104-: share implementation of ppc exception init 
This was really inconsistent, some implementations could touch PPCs
that didn't exist, others neglected to touch ones that did.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
87ac331e3f drm/nouveau/gr/gk104-: move rop_active_fbps init to nonctx 
Matches newer RM.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
4d3df19a8e drm/nouveau/bios/pll: check BIT table version before trying to parse it 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
2781c928b1 drm/nouveau/bios/pll: prevent oops when limits table can't be parsed 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Karol Herbst
d07a97e939 drm/nouveau/volt/gk104: round up in gk104_volt_set 
We always want a equal or higher voltage than the requested ones, otherwise
nouveau undervolts.

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
e976278ad2 drm/nouveau/fb/gm200: setup mmu debug buffer registers at init() 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
834b21f5e9 drm/nouveau/fb/gk20a,gm20b: setup mmu debug buffer registers at init() 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
99c5917253 drm/nouveau/fb/gf100-: allocate mmu debug buffers 
Later chipsets require setting this up both in FB and GR, so let's just
move the allocation to FB.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
917d95a86e drm/nouveau/fb: allow chipset-specific actions for oneinit() 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
06d4f26cc3 drm/nouveau/gr/gm200-: fix bad hardcoding of a max-tpcs-per-gpc value 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
734a0aa669 drm/nouveau/gr/gm200-: rop count == ltc count 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
c83e7d6836 drm/nouveau/gr/gm200: modify the mask when copying mmu settings from fb 
Appears to more closely match what RM does.

For GM20B, now also copying bit 12 from NV_PFB_MMU_CTRL as upcoming
changes will require it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
54aa38a8ad drm/nouveau/gr/gm200: move some code into init_gpc_mmu() hook 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
560e6da267 drm/nouveau/gr/gm200: make generate_main() static 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
64cb5a31f4 drm/nouveau/gr/gf100-: abstract fetching rop count 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
5ec3def735 drm/nouveau/gr/gf100-: rename magic_not_rop_nr to screen_tile_row_offset 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
933ad44594 drm/nouveau/gr/gf100-: remove hardcoded idle_timeout values 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
0cdc3fdfb7 drm/nouveau/fifo/gm107-: remove engines from mmu engine mapping array 
These are specified by PTOP on Maxwell GPUs.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
289e082706 drm/nouveau/fifo/gk104-: identify mmu engine ids for host faults 
It appears these don't map to PBDMAs (at least on Kepler, it may or may
be valid for Fermi - this hasn't been checked), but to runlists.

This drops the NVKM_ENGINE_FIFO data from the entries too, as resetting
all of PFIFO is *not* the way to handle such faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
e50d0237fc drm/nouveau/fifo/gk104-: implement support for PTOP fault info 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
91419acf78 drm/nouveau/fifo/gk104-: abstract mmu fault data structures 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
98ac3f061a drm/nouveau/fifo/gk104-: subclass func 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
e93e198d46 drm/nouveau/fifo/gk104-: use device info from top subdev 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
56d06fa29e drm/nouveau/core: remove pmc_enable argument from subdev ctor 
These are now specified directly in the MC subdev.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
d85e2a8dd8 drm/nouveau/mc/nv04: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
667e99ab23 drm/nouveau/mc/nv11: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
79360b7d5f drm/nouveau/mc/nv17: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
9199fbdbf8 drm/nouveau/mc/nv50: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
7354902001 drm/nouveau/mc/g84: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
e56f90fe17 drm/nouveau/mc/g98: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
88c0de2cdb drm/nouveau/mc/gt215: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
a6bb38e902 drm/nouveau/mc/gf100: define reset masks + intr cleanup 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
33537d6fdc drm/nouveau/mc/gk104: define reset masks + intr cleanup 
Engine fields have been removed, as they're specified by PTOP.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
921be10d85 drm/nouveau/mc: implement support for PTOP interrupt routing 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
583f8e4ea2 drm/nouveau/mc: implement support for PTOP reset info 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
70b01f07db drm/nouveau/mc: allow for local definition of reset bits 
With the addition of PTOP-specified reset bits, it makes more sense to
move the definitions here rather than in individual subdev
implementations.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
6defde5ab3 drm/nouveau/mc: add helper function to handle device reset 
This will be later extended to handle PTOP-specified reset masks as well
as the hardcoded ones.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
87f313e6e6 drm/nouveau/mc: rename struct nvkm_mc_intr to nvkm_mc_map 
This will also be used to define NV_PMC_ENABLE <-> subdev mappings in an
upcoming commit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
fb3e9c61ca drm/nouveau/top/gk104: initial implementation 
Ported from the code currently in engine/fifo/gk104.c.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
5f76f294d1 drm/nouveau/top: initial implementation 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Ben Skeggs
eaebfcc34e drm/nouveau/core: add top plumbing 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00
Karol Herbst
2e9a43f901 drm/nouveau/iccsense: configure sensors like nvidia does 
v2: rename ina209/ina219 read function

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2016-05-20 14:43:04 +10:00