Currently we emit semaphore synchronisation as if we were going to flip
using the target CS engine, but we then change our minds and do the flip
using the CPU. Consequently we write instructions to the ring but never
use them - even to the point of filling that ring up entirely and never
submitting a request.
The wrinkle in the ointment is that we have to tell a white lie to
pin-to-display for it to skip the synchronisation for mmioflips as we
will create a task specifically for that slow synchronisation. An oddity
of note is the discrepancy in requests that we tell to pin-display to
serialise to and that we then eventually wait upon. This is due to a
limitation in the i915_gem_object_sync() routine that will be lifted
later.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
The biggest user of i915_gem_object_get_page() is the relocation
processing during execbuffer. Typically userspace passes in a set of
relocations in sorted order. Sadly, we alternate between relocations
increasing from the start of the buffers, and relocations decreasing
from the end. However the majority of consecutive lookups will still be
in the same page. We could cache the start of the last sg chain, however
for most callers, the entire sgl is inside a single chain and so we see
no improve from the extra layer of caching.
v2: Avoid the double increment inside unlikely()
References: https://bugs.freedesktop.org/show_bug.cgi?id=88308
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
For the conversion to atomic. The pre_enable() hooks are called as part
of the crtc enable sequence, at which point the staged config was
already made effective. Furthermore, the function actually changes
hardware state, so it should anyway deal with current and not staged
config.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Now that we use a drm atomic state for the legacy modeset, it is
possible to get rid of the usage of intel_crtc->new_config in the
function intel_mode_max_pixclk().
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
../drivers/gpu/drm/i915/intel_pm.c:3185:45: warning: Initializer entry defined twice
../drivers/gpu/drm/i915/intel_pm.c:3185:52: also defined here
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Sometimes userspace wants a true overlay that is never clipped. In such
cases, we need to disable the destination colorkey. However, it is
currently unconditionally enabled in the overlay with no means of
disabling. So rectify that by always default to on, and extending the
UPDATE_ATTR ioctl to support explicit disabling of the colorkey.
This is contrast to the spite code which requires explicit enabling of
either the destination or source colorkey. Handling source colorkey is
still todo for the overlay. (Of course it may be worth migrating overlay
to sprite before then.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Modify the Gen9 SSEU device status logic to support Broxton.
Broxton reuses the Skylake power gate acknowledgment registers but
has at most 1 slice and 3 subslices. Broxton supports subslice
power gating within its single slice.
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Modify the Gen9 SSEU info initialization logic to support
Broxton. Broxton reuses the SKL fuse registers but has at most
1 slice and 6 EU per subslice.
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.
v2:
- add comment explaining how the problem with WC mapping manifests
(Daniel)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
The caching options for page table entries have remained the same as
Cherryview. This patch fixes it so the right code path is taken on BXT.
v2: Fix up commit message (Mike)
Signed-off-by: Sumit Singh <sumit.k.singh@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.
Motivated by Rodrigo's request to check FBC support on BXT.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
three commits, all cc: stable, to address Baytrail
suspend/resume issues.
* tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel:
drm/i915/vlv: remove wait for previous GFX clk disable request
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915/vlv: save/restore the power context base reg
Using the for_each_... macro should make the code a bit shorter and
easier to read. Also, when breaking out of the loop, the endpoint node
reference count needs to be decremented.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Using the for_each_... macro should make the code bit shorter and
easier to read. This patch also properly decrements the endpoint node
reference count before returning out of the loop.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Regression in commit 2caa80e72b
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sun Feb 22 11:38:36 2015 +0100
drm: Fix deadlock due to getconnector locking changes
If the drm_connector_find() call returns NULL, we should no longer
call drm_modeset_unlock() to avoid locking imbalance.
Signed-off-by: Tommi Rantala <tt.rantala@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
imx-drm limit fixes
Fix IPU IC downscaler to its hardware limitation of 4:1 and the
IPU DI pixel clock divider integer part to 8-bit.
* tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux:
gpu: ipu-v3: turns out the IPU can only downsize 4:1
gpu: ipu-v3: limit pixel clock divider to 8-bits
drm/radeon: programm the VCE fw BAR as well
drm/radeon: always dump the ring content if it's available
radeon: Do not directly dereference pointers to BIOS area.
drm/radeon/dpm: fix 120hz handling harder
1) support for "stolen mem" for splash-screen take-over
2) additional hdmi pixel clks
3) various pipe flush related fixes
4) support for snapdragon 410 (8x16)
5) support for DSI and dual-DSI
It includes one small patch to export tile-group functions (which was ack'd
by you), as these are used to explain to userspace dual-dsi configurations
(with left and right tile).
* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (24 commits)
drm/msm/mdp5: Enable DSI connector in msm drm driver
drm/msm: Initial add DSI connector support
drm/msm: Add split display interface
drm/msm/mdp5: Move *_modeset_init out of construct_encoder function
drm: export tile-group functions
drm/msm/mdp5: Remove CTL flush dummy bits
drm/msm/mdp5: Update headers (add CTL flush bits)
drm/msm/mdp5: Add hardware configuration for msm8x16
drm/msm/mdp5: Get SMP client list from mdp5_cfg
drm/msm/mdp5: Update headers (remove enum mdp5_client_id)
drm/msm/mdp5: Separate MDP5 domain from MDSS domain
drm/msm/mdp5: Update headers (introduce MDP5 domain)
drm/msm/dsi: Update generated DSI header file
drm/msm/mdp5: Fix PIPE source image size settings
drm/msm/mdp5: Update generated mdp5 header file with DSI support
drm/msm/mdp5: Add pingpong entry to mdp5 config table
drm/msm/mdp5: Make the intf connection in config module
drm/msm/mdp5: Add START signal to kick off certain pipelines
drm/msm/mdp5: Enhance operation mode for pipeline configuration
drm/msm/mdp5: Update generated header files
...
drm/panel: Changes for v4.1-rc1
This set of changes adds support for a whole bunch of new panels, mostly
simple ones. There's now also support for panels to provide display
timings rather than fixed modes, which should allow panels to work with
a larger number of display drivers. Eventually drivers should migrate to
this new interface and the fixed modes removed from panels.
There are also a couple of sparse fixes for the PS8622 and PS8625 bridge
drivers.
* tag 'drm/panel/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/panel: Add support for Ampire AM-800480R3TMQW-A1H 800x480 7" panel
of: Add vendor prefix for Ampire Co., Ltd.
drm/panel: Add display timing for HannStar HSD070PWW1
drm/panel: simple: Add display timing support
drm/panel: Add display timing support
drm/panel: Add support for OrtusTech COM43H4M85ULC panel
of: Add vendor prefix for Ortus Technology Co., Ltd.
drm/panel: Add bus format for Giantplus GPG482739QS5 panel
drm/panel: simple: Add support for AUO b101ean01 panel
drm/panel: simple: Add support for Innolux ZJ070NA-01P
drm/panel: simple: Add support for Innolux AT043TN24
drm/panel: simple: Add support for Shelly SCA07010-BFN-LNN
drm/panel: simple: Add support for Samsung LTN140AT29 panel
drm: Remove unused DRM_MODE_OBJECT_BRIDGE
drm/bridge: ptn3460: Fix sparse warnings
drm/bridge: ps8622: Fix sparse warnings
drm/bridge: Add I2C based driver for ps8622/ps8625 bridge
drm/tegra: Changes for v4.1-rc1
Perhaps the most noteworthy change in this set is the implementation of
a hardware VBLANK counter using host1x syncpoints. The SOR registers can
now be dumped via debugfs, which can be useful while debugging. The IOVA
address space maintained by the driver can also be dumped via debugfs.
Other than than, these changes are mostly cleanup work, such as making
register names more consistent or removing unused code (that was left
over after the atomic mode-setting conversion). There's also a fix for
eDP that makes the driver cope with firmware that already initialized
the display (such as the firmware on the Tegra-based Chromebooks).
* tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: sor: Reset during initialization
drm/tegra: gem: Return 64-bit offset for mmap(2)
drm/tegra: hdmi: Name register fields consistently
drm/tegra: hdmi: Resets are synchronous
drm/tegra: dc: Document tegra_dc_state_setup_clock()
drm/tegra: dc: Remove unused callbacks
drm/tegra: dc: Remove unused function
drm/tegra: dc: Use base atomic state helpers
drm/atomic: Add helpers for state-subclassing drivers
drm/tegra: dc: Implement hardware VBLANK counter
gpu: host1x: Export host1x_syncpt_read()
drm/tegra: sor: Dump registers via debugfs
drm/tegra: sor: Registers are 32-bit
drm/tegra: Provide debugfs file for the IOVA space
drm/tegra: dc: Check for valid parent clock
omapdrm changes for 4.1
* universal plane support
* refactoring to prepare work atomic modesetting work
* a lot of small fixes
* tag 'omapdrm-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (36 commits)
drm/omap: tiler: add hibernation callback
drm/omap: add hibernation callbacks
drm/omap: keep ref to old_fb
drm/omap: fix race conditon in DMM
drm/omap: fix race condition with dev->obj_list
drm/omap: do not use BUG_ON(!spin_is_locked(x))
drm/omap: only ignore DIGIT SYNC LOST for TV output
drm/omap: fix race with error_irq
drm/omap: use DRM_ERROR_RATELIMITED() for error irqs
drm/omap: stop connector polling during suspend
drm/omap: remove dummy PM functions
drm/omap: tiler: fix race condition with engine->async
drm/omap: fix plane's channel selection
drm/omap: fix TILER on OMAP5
drm/omap: handle incompatible buffer stride and pixel size
drm/omap: fix error handling in omap_framebuffer_create()
drm/omap: fix operation without fbdev
drm/omap: add a comment why locking is missing
drm/omap: add pin refcounting to omap_framebuffer
drm/omap: clear omap_obj->paddr in omap_gem_put_paddr()
...
The tracing infrastructure is adding a macro TRACE_SYSTEM_STRING, and
hit the following build failure:
In file included from include/trace/define_trace.h:90:0,
from drivers/gpu/drm/.//radeon/radeon_trace.h:209,
from drivers/gpu/drm/.//radeon/radeon_trace_points.c:9:
>> include/trace/ftrace.h:28:0: warning: "TRACE_SYSTEM_STRING" redefined
#define TRACE_SYSTEM_STRING __app(TRACE_SYSTEM_VAR,__trace_system_name)
Seems that the DRM folks have added their own use to the
TRACE_SYSTEM_STRING, with:
#define TRACE_SYSTEM_STRING __stringify(TRACE_SYSTEM)
Although, I can not find its use anywhere. I could simply use another
name, but if this macro is not being used, it should be removed.
Link: http://lkml.kernel.org/r/20150402123736.01eda052@gandalf.local.home
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Tested-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
