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Author SHA1 Message Date
Linus Torvalds
8582976acc Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 
Pull phy updates from Vinod Koul:
 "New Support:

   - Qualcomm Milos Synopsys eUSB2 PHY, SM8750 QMP phy support, M31
     eUSB2 PHY driver

   - Samsung Exynos990 usbdrd phy, Exynos7870 MIPI phy support

   - Renesas RZ/V2N usb2-phy support

  Updates:

   - Bulk Yaml binding conversion By Rob H (too many to be listed)

   - cadence: Sierra PCIe, USB PHY multilink configuration support

   - Qualcomm refactoring of UFS PHY reset and UFS driver support for
     phy calibrate API"

* tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (74 commits)
  phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
  dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
  dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
  dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
  dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
  phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870
  phy: qcom: phy-qcom-snps-eusb2: Update init sequence per HPG 1.0.2
  phy: qcom: phy-qcom-snps-eusb2: Add missing write from init sequence
  dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
  dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
  phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal
  phy: rockchip-pcie: Enable all four lanes if required
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
  phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750
  phy: qcom: m31-eusb2: drop registration printk
  phy: qcom: m31-eusb2: fix match data santity check
  phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P
  phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers
  dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
  phy: mediatek: tphy: Cleanup and document slew calibration
  ...
 2025-08-01 12:31:50 -07:00
Frank Li
5d005cf799 dt-bindings: mfd: Convert lpc1850-creg-clk, pc1850-dmamux and phy-lpc18xx-usb-otg to YAML format 
Combine the following separate plain text based bindings to YAML:

  lpc1850-creg-clk.txt
  pc1850-dmamux.txt
  phy-lpc18xx-usb-otg.txt

Additional changes:

- remove label in example.
- remove dmamux consumer in example.
- remove clock consumer in example.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250602143612.943516-1-Frank.Li@nxp.com
Signed-off-by: Lee Jones <lee@kernel.org>
 2025-07-24 11:26:58 +01:00
Rob Herring (Arm)
4c3d05da59 dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema 
Convert the Broadcom Stingray USB PHY binding to DT schema format. It's
a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20250627220126.214577-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-07-22 18:58:31 +05:30
Rob Herring (Arm)
99dd7faeb7 dt-bindings: phy: Convert ti,da830-usb-phy to DT schema 
Convert the TI DA830 USB PHY binding to DT schema format. Add "clocks"
and "clock-names" which are already in use. As they are always present,
make them required as well.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: David Lechner <david@lechnology.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250627220107.214162-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-07-22 18:58:02 +05:30
Krzysztof Kozlowski
a91ec5efde dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example 
Examples should not have the 'status' property and 'okay' is anyway by
default.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250701063636.23872-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-07-22 18:49:00 +05:30
Liu Ying
429efeb190 dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties 
assigned-clock* properties can be used by default now, so allow them.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250707-dt-bindings-phy-mixel-mipi-dsi-phy-allow-assign-clock-properties-v1-1-5e34b257e1ef@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-07-22 18:48:31 +05:30
Luca Weiss
bb39f49a43 dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY 
Document the Synopsys eUSB2 PHY on the Milos SoC by using the SM8550 as
fallback.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-eusb-phy-v3-2-6c3224085eb6@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-07-22 18:05:45 +05:30
Ziyue Zhang
dfef90f298 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615 
QCS615 pcie phy only use 5 clocks, which are aux, cfg_ahb, ref,
ref_gen, pipe. So move "qcom,qcs615-qmp-gen3x1-pcie-phy" compatible
from 6 clocks' list to 5 clocks' list.

Fixes: 1e889f2bd8 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS615 QMP PCIe PHY Gen3 x1")
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250703095630.669044-2-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-07-22 17:53:11 +05:30
Luca Weiss
db9f3e3ff9 dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values 
The reset default tuning value depends on the PMIC, so remove them from
the doc since they're not accurate for all PMICs.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250617-eusb2-repeater-tuning-v2-1-ed6c484f18ee@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-26 16:36:36 -07:00
Geert Uytterhoeven
05c6f31991 dt-bindings: phy: apm,xgene-phy: Remove trailing whitespace 
Remove trailing whitespace which hurts my eyes.

Fixes: 65ad0d068c ("dt-bindings: phy: Convert apm,xgene-phy to DT schema")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5b8e9b4f645bcac9d50059e513abba4db7e1aaea.1750771156.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-26 16:30:10 -07:00
Wesley Cheng
1166a2ca09 dt-bindings: phy: Add the M31 based eUSB2 PHY bindings 
On SM8750, the M31 eUSB2 PHY is being used to support USB2. Add the
binding definition for the PHY driver.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-2-d58de3b41d34@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 21:58:52 +05:30
Wesley Cheng
439cdb309c dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHY 
Add an entry to the compatible field for SM8750 for the QMP combo PHY.
This handles the USB3 path for SM8750.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-1-d58de3b41d34@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 21:58:52 +05:30
Lad Prabhakar
00399bbe02 dt-bindings: phy: renesas,usb2-phy: Document RZ/V2N SoC support 
Document support for the USB2.0 phy found on the Renesas RZ/V2N
(R9A09G056) SoC. The USB2.0 phy is functionally identical to that on the
RZ/V2H(P) SoC, so no driver changes are needed. The existing
`renesas,usb2-phy-r9a09g057` compatible will be used as a fallback
for the RZ/V2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250528133858.168582-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 20:06:04 +05:30
Rob Herring (Arm)
4dcf1632d6 dt-bindings: phy: Convert Marvell MVEBU PHYs to DT schema 
Convert the Marvell Armada-375 USB and MVEBU SATA PHY binding to DT
schema format. It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20250607212609.743346-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 20:05:04 +05:30
Rob Herring (Arm)
a5aa04619e dt-bindings: phy: Convert marvell,armada-380-comphy to DT schema 
Convert the Marvell Armada 38x combo PHY binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20250607212541.742427-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 20:04:31 +05:30
Rob Herring (Arm)
222bb02ee6 dt-bindings: phy: Convert ti,keystone-usbphy to DT schema 
Convert the TI Keystone USB PHY binding to DT schema format. Drop the
"#address-cells" and "#size-cells" properties which don't make sense
without any child nodes.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212641.744683-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
35b629b28a dt-bindings: phy: Convert ti,dm816x-usb-phy to DT schema 
Convert the TI DM816x USB PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212634.744373-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
ea54c9d157 dt-bindings: phy: Convert st,spear1310-miphy to DT schema 
Convert the ST SPEAr MIPHY PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212629.744191-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
3ed7be1275 dt-bindings: phy: Convert qca,ar7100-usb-phy to DT schema 
Convert the Qualcomm-Atheros AR7100 USB PHY binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212625.744008-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
90647aa7e6 dt-bindings: phy: Convert motorola,mapphone-mdm6600 to DT schema 
Convert the Motorola Mapphone MDM6600 USB PHY binding to DT schema
format. It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212621.743859-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
351d6b70c1 dt-bindings: phy: Convert motorola,cpcap-usb-phy to DT schema 
Convert the Motorola CPCAP PMIC USB PHY binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212616.743674-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
fbcc493763 dt-bindings: phy: Convert marvell,mmp2-usb-phy to DT schema 
Convert the Marvell MMP2 USB PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212613.743515-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:02 +05:30
Rob Herring (Arm)
50355ac70d dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema 
Convert the Marvell CP110 combo PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212605.743176-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
08a9bc357a dt-bindings: phy: Convert marvell,berlin2-usb-phy to DT schema 
Convert the Marvell Berlin2 USB PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212554.742884-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
f4b522ce6a dt-bindings: phy: Convert marvell,berlin2-sata-phy to DT schema 
Convert the Marvell Berlin2 SATA PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212545.742617-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
85d6af3b73 dt-bindings: phy: Convert lantiq,ase-usb2-phy to DT schema 
Convert the Lantiq XWAY USB PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212537.742287-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
66acaf8f6b dt-bindings: phy: Convert img,pistachio-usb-phy to DT schema 
Convert the Imagination Pistachio USB PHY binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212531.742082-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
7cc5efcd94 dt-bindings: phy: Convert hisilicon,inno-usb2-phy to DT schema 
Convert the HiSilicon INNO USB2 PHY binding to DT schema format. It's a
straight forward conversion.

Add the undocumented "hisilicon,hi3798mv100-usb2-phy" compatible.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212527.741915-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
40f1d82142 dt-bindings: phy: Convert hisilicon,hi6220-usb-phy to DT schema 
Convert the HiSilicon HI6220 USB PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212524.741770-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
1fac100a4d dt-bindings: phy: Convert hisilicon,hix5hd2-sata-phy to DT schema 
Convert the HiSilicon HIX5HD2 SATA PHY binding to DT schema format. It's
a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212520.741588-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
6725c334e9 dt-bindings: phy: Convert brcm,sr-pcie-phy to DT schema 
Convert the Broadcom Stingray PCIe PHY binding to DT schema format. It's
a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212508.741193-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
f151f3a6eb dt-bindings: phy: Convert brcm,ns2-drd-phy to DT schema 
Convert the Broadcom NS2 USB2 PHY binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212456.740697-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:01 +05:30
Rob Herring (Arm)
65ad0d068c dt-bindings: phy: Convert apm,xgene-phy to DT schema 
Convert the APM X-Gene PHY binding to DT schema format. It's a straight
forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212424.739972-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:59:00 +05:30
Kaustabh Chakraborty
2ac5840594 dt-bindings: phy: samsung,mipi-video-phy: document exynos7870 MIPI phy 
The Exynos7870 MIPI PHY device contains one DSIM PHY block and three
CSIS PHY blocks. It also requires two sysregs, one for display, and the
other for cameras. Document this device.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250612-exynos7870-mipi-phy-v1-1-3fff0b62d9d3@disroot.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-15 19:37:34 +05:30
Igor Belwon
9f77d234c1 dt-bindings: phy: samsung,usb3-drd-phy: Add exynos990 compatible 
Add a compatible for the exynos990-usbdrd-phy. The PHY is compatible with
the older exynos5420 design (two clocks) when running in highspeed mode.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20250515-usb-resends-may-15-v3-1-ad33a85b6cee@mentallysanemainliners.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-06-14 17:49:09 +05:30
Kever Yang
abf55cdf9c dt-bindings: phy: rockchip,inno-usb2phy: add rk3562 
Add compatible for the USB2 phy in the Rockchip RK3562 SoC.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 12:20:39 +01:00
Heiko Stuebner
d78b565371 dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible 
Add compatible for the USB2 phy in the Rockchip RK3036 SoC.

Apart from some bits that got swapped around in the phy registers, the
block is nearly the same as the one on the rk3128.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 12:19:29 +01:00
Lad Prabhakar
9c4fbefc96 dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC 
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC.

RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it
needs additional configuration to be done as compared RZ/G2L USB2.0 phy.
To handle this difference a SoC specific compat string is added for
RZ/V2H(P) SoC.

Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets`
property and has two clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 12:14:59 +01:00
Lad Prabhakar
31eebeef8c dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family 
The RZ/G2L family requires two clocks for USB2 PHY, which are already
defined in the DTSI files. Add a constraint in the DT binding document
to ensure validation with `dtbs_check`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 12:14:58 +01:00
Ivaylo Ivanov
e4c9a7b475 dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 support 
Document support for Exynos2200. As the USBDRD 3.2 4nm controller
consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will
be handled by external drivers, define only the bus clocked used
by the link controller.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 11:43:37 +01:00
Ivaylo Ivanov
59cf754607 dt-bindings: phy: add exynos2200 eusb2 phy support 
Document the exynos2200 eUSB2 compatible. Unlike the currently documented
Qualcomm SoCs, the driver doesn't make use of reset lines for reset
control and uses more clocks.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 11:43:37 +01:00
Rob Herring (Arm)
1d6fc048b8 dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schema 
Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the
example to the GRF binding as that has the complete block.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 11:16:28 +01:00
Xu Yang
7325e0995f dt-bindings: phy: imx8mq-usb: add imx95 tuning support 
The parameter value of below 3 properties are USB PHY specific. i.MX8MP
and i.MX95 USB PHY has different meanings. This will enlarge parameters
value and add constraints for them.

 - fsl,phy-tx-vref-tune-percent
 - fsl,phy-tx-rise-tune-percent
 - fsl,phy-comp-dis-tune-percent

Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 11:16:04 +01:00
Xu Yang
5b3a91b207 dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt property 
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in
register PHY_CTRL3 bit[31:29].

  011: Corresponds to a launch amplitude of 1.12 V.
  010: Corresponds to a launch amplitude of 1.04 V.
  000: Corresponds to a launch amplitude of 0.88 V.

After updated:

  011: Corresponds to a launch amplitude of 0.844 V.
  100: Corresponds to a launch amplitude of 1.008 V.
  101: Corresponds to a launch amplitude of 1.156 V.

This will correct it accordingly.

Fixes: b2e75563dc ("dt-bindings: phy: imx8mq-usb: add phy tuning properties")
Cc: stable@vger.kernel.org
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 11:16:04 +01:00
AngeloGioacchino Del Regno
1b1e949924 dt-bindings: phy: mediatek,tphy: Add support for MT6893 
Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC: this chip integrates a MediaTek generic T-PHY version 2.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 09:44:35 +01:00
AngeloGioacchino Del Regno
fe750a871d dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893 
Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI
PHY found in this chip is fully compatible with the one found in
the MT8183 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 09:44:35 +01:00
Rob Herring (Arm)
2063eedf3c dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schema 
Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the
missing "power-domains" property and "port" and "orientation-switch"
properties in the child nodes.

Omit the previously deprecated properties as they aren't used anywhere.

Drop the 2nd example which was pretty much identical to the 1st example.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 09:32:02 +01:00
Siddharth Vadapalli
e00c9aea31 dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMII 
The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the
bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value
of "12" while the existing maximum allowed PHY TYPE is "9", switch back to
using "enum" property in the bindings to account for this discontinuity.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 09:26:05 +01:00
Frank Wunderlich
b484b25a48 dt-bindings: phy: mtk-xs-phy: support type switch by pericfg 
Add support for type switch by pericfg register between USB3/PCIe.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250422132438.15735-5-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 09:24:44 +01:00
Frank Wunderlich
117d09e283 dt-bindings: phy: mtk-xs-phy: Add mt7988 compatible 
Add compatible for xs-phy on mt7988.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250422132438.15735-4-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2025-05-14 09:24:43 +01:00