4 Commits

Author	SHA1	Message	Date
Charlene Liu	f82c916c41	drm/amd/display: add some parameters to validate bandwidth functions ... required for new checks. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-06-22 09:34:13 -05:00
Charlene Liu	8bb3d7e7b5	drm/amd/display: used optimum VSTARTUP instead of MaxVStartup ... [Description] Features that are desirable for minimizing the Global Sync Period: DRR and lateflip Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-06-22 09:34:12 -05:00
Jun Lei	6ba117404e	drm/amd/display: fix pstate allow handling in dcn2 ... [why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support at both min and max mpc combine rather than just min clock manager needs to update current to new pstate support before sending to pplib/smu Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-06-22 09:34:08 -05:00
Harry Wentland	728c06986a	drm/amd/display: Add DCN2 changes to DML ... Update DML (Display Mode Lib) to support DCN2 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-06-21 18:59:34 -05:00