The ASPEED AST27XX interrupt controller(INTC) contains second level and
third level interrupt controller.
INTC0:
The second level INTC, which used to assert GIC if interrupt in INTC1 asserted.
INTC1_x:
The third level INTC, which used to assert INTC0 if interrupt in modules
of INTC asserted.
The relationship is like the following:
+-----+ +-------+ +---------+---module0
| GIC |---| INTC0 |--+--| INTC1_0 |---module1
| | | | | | |---...
+-----+ +-------+ | +---------+---module31
|
| +---------+---module0
+---| INTC1_1 |---module1
| | |---...
| +---------+---module31
...
| +---------+---module0
+---| INTC1_5 |---module1
| |---...
+---------+---module31
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/all/20241016022410.1154574-2-kevin_chen@aspeedtech.com
