Commit Graph

586 Commits

Author SHA1 Message Date
Linus Torvalds
bfdf35c5dc Merge tag 'dmaengine-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
 "A fairly small update for the dmaengine subsystem. This has a new ARM
  dmaengine driver and couple of new device support and few driver
  changes:

  New support:
   - Renesas RZ/V2H(P) dma support for r9a09g057
   - Arm DMA-350 driver
   - Tegra Tegra264 ADMA support

  Updates:
   - AMD ptdma driver code removal and optimizations
   - Freescale edma error interrupt handler support"

* tag 'dmaengine-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (27 commits)
  dmaengine: idxd: Remove unused pointer and macro
  arm64: dts: renesas: r9a09g057: Add DMAC nodes
  dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
  dmaengine: sh: rz-dmac: Allow for multiple DMACs
  irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req()
  dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
  dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
  dmaengine: idxd: Narrow the restriction on BATCH to ver. 1 only
  dmaengine: ti: Add NULL check in udma_probe()
  fsldma: Set correct dma_mask based on hw capability
  dmaengine: idxd: Check availability of workqueue allocated by idxd wq driver before using
  dmaengine: xilinx_dma: Set dma_device directions
  dmaengine: tegra210-adma: Add Tegra264 support
  dt-bindings: Document Tegra264 ADMA support
  dmaengine: dw-edma: Add HDMA NATIVE map check
  dmaegnine: fsl-edma: add edma error interrupt handler
  dt-bindings: dma: fsl-edma: increase maxItems of interrupts and interrupt-names
  dmaengine: ARM_DMA350 should depend on ARM/ARM64
  dt-bindings: dma: qcom,bam: Document dma-coherent property
  dmaengine: Add Arm DMA-350 driver
  ...
2025-06-05 08:49:30 -07:00
Fabrizio Castro
22228b933c dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
Renesas RZ/G2L family of SoCs, but there are some differences:
* It only uses one register area
* It only uses one clock
* It only uses one reset
* Instead of using MID/IRD it uses REQ No
* It is connected to the Interrupt Control Unit (ICU)

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250423143422.3747702-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 15:30:40 +01:00
Fabrizio Castro
ec52f10a31 dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
Make sure we don't allow for the clocks, clock-names, resets,
reset-names. and power-domains properties for the Renesas
RZ/A1H SoC because its DMAC doesn't have clocks, resets,
and power domains.

Fixes: 209efec19c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250423143422.3747702-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 15:30:40 +01:00
Sheetal
b81cd165e4 dt-bindings: Document Tegra264 ADMA support
Add Tegra264 ADMA support to the device tree bindings documentation.
The Tegra264 ADMA hardware supports 64 DMA channels and requires
specific register configurations.

Signed-off-by: Sheetal <sheetal@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250512050010.1025259-2-sheetal@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 14:47:22 +01:00
Charan Pedumuru
d2c9d35480 dt-bindings: dma: nvidia,tegra20-apbdma: convert text based binding to json schema
Update text binding to YAML.
Changes during conversion:
- Add a fallback for "nvidia,tegra30-apbdma" as it is
  compatible with the IP core on "nvidia,tegra20-apbdma".
- Update examples and include appropriate file directives to resolve
  errors identified by `dt_binding_check` and `dtbs_check`.

Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250507-nvidea-dma-v4-2-6161a8de376f@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08 22:11:39 +02:00
Joy Zou
a9ea01f284 dt-bindings: dma: fsl-edma: increase maxItems of interrupts and interrupt-names
The edma controller support optional error interrupt, so update interrupts
and interrupt-names's maxItems.

Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250407-edma_err-v2-1-9d7e5b77fcc4@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-23 18:42:46 +05:30
Kaushal Kumar
5965fd614b dt-bindings: dma: qcom,bam: Document dma-coherent property
Qualcomm BAM DMA controller has DMA-coherent support so define it in the
properties section.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Link: https://lore.kernel.org/r/20250423063054.28795-3-quic_kaushalk@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-23 18:42:46 +05:30
Robin Murphy
c4771efa84 dt-bindings: dma: Add Arm DMA-350
Arm CoreLink DMA-350 is a pleasantly straightforward DMA controller
which, although highly configurable, lends itself to a simple binding
thanks to plenty of self-describing ID registers.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/15830b2a8ff9721e364f30f93ea3993139b0103b.1741780808.git.robin.murphy@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-17 20:47:39 +05:30
Linus Torvalds
91e5bfe317 Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
 "The dmaengine subsystem updates for this cycle consist of a new driver
  (Microchip) along with couple of yaml binding conversions, core api
  updates and bunch of driver updates etc.

  New HW support:

   - Microchip sama7d65 dma controller

   - Yaml conversion of atmel dma binding and Freescale Elo DMA
     Controller binding

  Core:

   - Remove device_prep_dma_imm_data() API as users are removed

   - Reduce scope of some less frequently used DMA request channel APIs
     with aim to cleanup these in future

  Updates:

   - Drop Fenghua Yu from idxd maintainers, as he changed jobs

   - AMD ptdma support for multiqueue and ae4dma deprecated PCI IDs
     removal"

* tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (29 commits)
  dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality
  dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number
  dmaengine: ae4dma: Remove deprecated PCI IDs
  dmaengine: Remove device_prep_dma_imm_data from struct dma_device
  dmaengine: ti: edma: support sw triggered chans in of_edma_xlate()
  dmaengine: ti: k3-udma: Enable second resource range for BCDMA and PKTDMA
  dmaengine: fsl-edma: free irq correctly in remove path
  dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister
  dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
  dmaengine: dmatest: Fix dmatest waiting less when interrupted
  dt-bindings: dma: Convert fsl,elo*-dma to YAML
  dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
  dmaengine: Fix typo in comment
  dmaengine: ti: k3-udma-glue: Drop skip_fdq argument from k3_udma_glue_reset_rx_chn
  dmaengine: bcm2835-dma: fix warning when CONFIG_PM=n
  dt-bindings: dma: fsl,edma: Add i.MX94 support
  dt-bindings: dma: atmel: add microchip,sama7d65-dma
  dmaengine: img-mdc: remove incorrect of_match_ptr annotation
  dmaengine: idxd: Delete unnecessary NULL check
  dmaengine: pxa: Enable compile test
  ...
2025-04-01 12:57:14 -07:00
Inochi Amaoto
6ec29d4086 dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
A RISC-V platform can have both DMA coherent/noncoherent devices.
Since the RISC-V architecture is marked coherent, devices should
be marked as noncoherent when coherent devices exist.

Add dma-noncoherent property for snps,dw-axi-dmac device. It will
be used on SG2044, and it has other coherent devices.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250303065649.937233-1-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11 02:21:44 +05:30
J. Neuschäfer
1fe283e850 dt-bindings: dma: Convert fsl,elo*-dma to YAML
The devicetree bindings for Freescale DMA engines have so far existed as
a text file. This patch converts them to YAML, and specifies all the
compatible strings currently in use in arch/powerpc/boot/dts.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250308-ppcyaml-dma-v4-1-20392ea81ec6@posteo.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11 02:04:15 +05:30
Frank Li
964c032d1d dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
Add compatible string for all i.MX8 chips, which is backward compatible
with i.MX28. Set it to fall back to "fsl,imx28-dma-apbh".

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250307215100.3257649-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11 02:02:46 +05:30
Frank Li
34436106af dt-bindings: dma: fsl,edma: Add i.MX94 support
Add support for the i.MX94 DMA controllers. The SoC includes two DMA
controllers: one compatible with i.MX93 eDMA3 and another compatible with
i.MX95 eDMA5.

Add compatible string "fsl,imx94-edma3" with fallback to "fsl,imx93-edma3".
Add compatible string "fsl,imx94-edma5" with fallback to "fsl,imx95-edma5".

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250221222153.405285-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-27 12:36:43 +05:30
Ryan Wanner
e19ba02eeb dt-bindings: dma: atmel: add microchip,sama7d65-dma
Add microchip,sama7d65-dma compatible string to DT bindings
documentation.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/8b69f0c6d8955790edcdbe5d1e205b43dedb99ff.1739555984.git.Ryan.Wanner@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-27 12:35:46 +05:30
Michal Simek
f0ceedd52a dt-bindings: xilinx: Deprecate header with firmware constants
Firmware contants do not fit the purpose of bindings because they are not
independent IDs for abstractions. They are more or less just contants which
better to wire via header with DT which is using it.
That's why add deprecated message to dt binding header and also update
existing dt bindings not to use macros from the header  and replace them by
it's value. Actually value is not relevant because it is only example.

The similar changes have been done by commit 9d92925768 ("dt-bindings:
pinctrl: samsung: deprecate header with register constants").

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2a6f0229522327939e6893565e540b75f854a37b.1738600745.git.michal.simek@amd.com
2025-02-21 07:58:35 +01:00
Durai Manickam KR
a54ec77039 dt-bindings: dma: convert atmel-dma.txt to YAML
Add a description, required properties, appropriate compatibles and
missing properties like clocks and clock-names which are not defined in
the text binding for all the SoCs that are supported by microchip.
Update the text binding name `atmel-dma.txt` to
`atmel,at91sam9g45-dma.yaml` for the files which reference to
`atmel-dma.txt`. Drop Tudor name from maintainers.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250203-test-v4-1-a9ec3eded1c7@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10 19:11:59 +05:30
Charan Pedumuru
5d6670033a dt-bindings: dma: atmel: Convert to json schema
Convert old text based binding to json schema.
Changes during conversion:
- Add the required properties `clock` and `clock-names`, which were
  missing in the original binding.
- Add a fallback for `microchip,sam9x7-dma` and `microchip,sam9x60-dma`
  as they are compatible with the dma IP core on `atmel,sama5d4-dma`.
- Update examples and include appropriate file directives to resolve
  errors identified by `dt_binding_check` and `dtbs_check`.

Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241205-xdma-v1-1-76a4a44670b5@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 16:07:00 +05:30
Ken Sloat
54e09c8e2d dt-bindings: dma: st-stm32-dmamux: Add description for dma-cell values
The dma-cell values for the stm32-dmamux are used to craft the DMA spec
for the actual controller. These values are currently undocumented
leaving the user to reverse engineer the driver in order to determine
their meaning. Add a basic description, while avoiding duplicating
information by pointing the user to the associated DMA docs that
describe the fields in depth.

Signed-off-by: Ken Sloat <ksloat@cornersoftsolutions.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241206115018.1155149-1-ksloat@cornersoftsolutions.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 16:06:23 +05:30
David Lechner
06d5363296 dt-bindings: dma: adi,axi-dmac: deprecate adi,channels node
Deprecate the adi,channels node in the adi,axi-dmac binding. Prior to
IP version 4.3.a, this information was required. Since then, there are
memory-mapped registers that can be read to get the same information.

Acked-by: Nuno Sa <nuno.sa@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-2-7b994710c43f@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:48:08 +05:30
David Lechner
788726fcea dt-bindings: dma: adi,axi-dmac: convert to yaml schema
Convert the AXI DMAC bindings from .txt to .yaml.

Acked-by: Nuno Sa <nuno.sa@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-1-7b994710c43f@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:48:08 +05:30
Mohan Kumar D
762b37fc6a dt-bindings: dma: Support channel page to nvidia,tegra210-adma
Multiple ADMA Channel page hardware support has been added from
TEGRA186 and onwards. Update the DT binding to use any of the
ADMA channel page address space region.

Signed-off-by: Mohan Kumar D <mkumard@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241217074358.340180-2-mkumard@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:34:04 +05:30
Vaishnav Achath
775363772f dt-bindings: dma: ti: k3-bcdma: Add J722S CSI BCDMA
J722S CSI BCDMA is similar to J721S2 CSI BCDMA and supports both RX and TX
channels but has a different PSIL thread base ID which is currently
handled in k3-udma driver. Add an entry for J722S CSIRX BCDMA.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241127101627.617537-2-vaishnav.a@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:32:21 +05:30
Larisa Grigore
57eeb0a566 dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string
Introduce the compatible strings 'nxp,s32g2-edma' and 'nxp,s32g3-edma' to
enable the support for the eDMAv3 present on S32G2/S32G3 platforms.

The S32G2/S32G3 eDMA architecture features 32 DMA channels. Each of the
two eDMA instances is integrated with two DMAMUX blocks.

Another particularity of these SoCs is that the interrupts are shared
between channels in the following way:
- DMA Channels 0-15 share the 'tx-0-15' interrupt
- DMA Channels 16-31 share the 'tx-16-31' interrupt
- all channels share the 'err' interrupt

Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241219102415.1208328-4-larisa.grigore@oss.nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:14:13 +05:30
Melody Olvera
24947be1c7 dt-bindings: dma: qcom,gpi: Document the sm8750 GPI DMA engine
Document the GPI DMA engine on the sm8750 platform.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241021230500.2632527-1-quic_molvera@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11 17:35:08 +05:30
Csókás, Bence
fdcdcc5715 dt-bindings: dmaengine: Add Allwinner suniv F1C100s DMA
Add compatible string for Allwinner suniv F1C100s DMA.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
[ csokas.bence: Reimplemented Mesih Kilinc's binding in YAML ]
Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
Link: https://lore.kernel.org/r/20241122161128.2619172-4-csokas.bence@prolan.hu
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11 17:35:03 +05:30
Konrad Dybcio
bf9b083455 dt-bindings: dma: qcom,gpi: Add SA8775P compatible
Add a compatible for the GPI DMA controller on SA8775P.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241108-topic-sa8775_dma2-v1-1-1d3b0d08d153@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02 22:24:48 +05:30
Viken Dadhaniya
794dae8987 dt-bindings: dma: qcom,gpi: Add QCS8300 compatible
Document compatible for GPI DMA controller on QCS8300 platform.

Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241112041252.351266-1-quic_vdadhani@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02 22:16:03 +05:30
Viken Dadhaniya
c841f9909b dt-bindings: dma: qcom,gpi: Add QCS615 compatible
Document compatible for GPI DMA controller on QCS615 platform.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20241115092854.1877369-1-quic_vdadhani@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02 22:12:34 +05:30
Linus Torvalds
7536c1a50e Merge tag 'dmaengine-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
 "New hardware support:

   - Qualcomm SAR2130P GPI dma support

   - Sifive PIC64GX pdma support

   - Rcar r7s72100 support and associated updates

  Updates:

   - STM32 DMA3 updates for packing/unpacking mode and prevention of
     additional xfers

   - Simplification of devm_acpi_dma_controller_register() and associate
     cleanup including headers

   - loongson prefix renames

   - Switch back to platform_driver::remove() subsystem update"

* tag 'dmaengine-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
  dmaengine: loongson2-apb: Rename the prefix ls2x to loongson2
  dt-bindings: dma: sifive pdma: Add PIC64GX to compatibles
  dmaengine: fix typo in the comment
  dmaengine: stm32-dma3: clamp AXI burst using match data
  dmaengine: stm32-dma3: prevent LL refactoring thanks to DT configuration
  dt-bindings: dma: stm32-dma3: prevent additional transfers
  dmaengine: stm32-dma3: refactor HW linked-list to optimize memory accesses
  dmaengine: stm32-dma3: prevent pack/unpack thanks to DT configuration
  dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode
  dmaengine: idxd: Move DSA/IAA device IDs to IDXD driver
  dt-bindings: dma: qcom,gpi: Add SAR2130P compatible
  dmaengine: Switch back to struct platform_driver::remove()
  dmaengine: ep93xx: Fix unsigned compared against 0
  dmaengine: acpi: Clean up headers
  dmaengine: acpi: Simplify devm_acpi_dma_controller_register()
  dmaengine: acpi: Drop unused devm_acpi_dma_controller_free()
  dmaengine: sh: rz-dmac: add r7s72100 support
  dt-bindings: dma: rz-dmac: Document RZ/A1H SoC
2024-11-27 13:25:47 -08:00
Pierre-Henry Moussay
7655ec4d0d dt-bindings: dma: sifive pdma: Add PIC64GX to compatibles
PIC64GX is compatible as out of order DMA capable, just like the MPFS
version, therefore we add it with microchip,mpfs-pdma as a fallback

Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240930095449.1813195-10-pierre-henry.moussay@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 23:11:11 +05:30
Amelie Delaunay
e18a983023 dt-bindings: dma: stm32-dma3: prevent additional transfers
Some devices require a single transfer. For example, reading FMC ECC status
registers does not support multiple transfers.
Add the possibility to prevent additional transfers, by setting bit 17 of
the 'DMA transfer requirements' bit mask.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-4-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 22:51:45 +05:30
Amelie Delaunay
689f05586e dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode
When source data width/burst and destination data width/burst are
different, data are packed or unpacked in DMA3 channel FIFO.
Data are pushed out from DMA3 channel FIFO when the destination burst
length (= data width * burst) is reached.
If the channel is stopped before the transfer end, and if some bytes are
packed/unpacked in the DMA3 channel FIFO, these bytes are lost.
Indeed, DMA3 channel FIFO has no flush capability, only reset.
To avoid potential bytes lost, pack/unpack must be prevented by setting
memory data width/burst equal to peripheral data width/burst.
Memory accesses will be penalized. But it is the only way to avoid bytes
lost.

Some devices (e.g. cyclic RX like UART) need this, so add the possibility
to prevent pack/unpack feature, by setting bit 16 of the 'DMA transfer
requirements' bit mask.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-1-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 22:51:44 +05:30
Dmitry Baryshkov
e7a614cc88 dt-bindings: dma: qcom,gpi: Add SAR2130P compatible
Document compatible for GPI DMA controller on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-dma-v1-1-e6aa6789f116@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 22:32:16 +05:30
Wolfram Sang
209efec19c dt-bindings: dma: rz-dmac: Document RZ/A1H SoC
Document the Renesas RZ/A1H DMAC block. This one does not have clocks,
resets and power domains. Update the bindings accordingly. Introduce a
generic name in the header to make future additions easier.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20241007110200.43166-7-wsa+renesas@sang-engineering.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-14 23:11:33 +05:30
Rob Herring (Arm)
a6fa1f9e32 dt-bindings: Fix array property constraints
Schemas for array properties should only have 1 level of array
constraints (e.g. items, maxItems, minItems). Sometimes the old
encoding of all properties into a matrix leaked into the schema, and
didn't matter for validation. Now the inner constraints are just
silently ignored as json-schema array keywords are ignored on scalar
values.

Generally, keep the inner constraints and drop the outer "items". With
gicv3 "mbi-alias" property, it is more appropriately a uint32 or uint64
as it is an address and size depends on "#address-cells".

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240925232409.2208515-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2024-10-01 21:17:00 -05:00
Linus Torvalds
075dbe9f6e Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC update from Arnd Bergmann:
 "Convert ep93xx to devicetree

  This concludes a long journey towards replacing the old board files
  with devictree description on the Cirrus Logic EP93xx platform.

  Nikita Shubin has been working on this for a long time, for details
  see the last post on

    https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/"

* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
  dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples
  MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer
  soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config
  net: cirrus: use u8 for addr to calm down sparse
  dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0
  dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe()
  pinctrl: ep93xx: Fix raster pins typo
  spi: ep93xx: update kerneldoc comments for ep93xx_spi
  clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()
  clk: ep93xx: add module license
  dmaengine: cirrus: remove platform code
  ASoC: cirrus: edb93xx: Delete driver
  ARM: ep93xx: soc: drop defines
  ARM: ep93xx: delete all boardfiles
  ata: pata_ep93xx: remove legacy pinctrl use
  pwm: ep93xx: drop legacy pinctrl
  ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
  ARM: dts: ep93xx: Add EDB9302 DT
  ARM: dts: ep93xx: add ts7250 board
  ARM: dts: add Cirrus EP93XX SoC .dtsi
  ...
2024-09-26 12:00:25 -07:00
Linus Torvalds
8874d92b57 Merge tag 'dmaengine-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
 "Unusually, more new driver and device support than updates. Couple of
  new device support, AMD, Rcar, Intel and New drivers in Freescale,
  Loonsoon, AMD and LPC32XX with DT conversion and mode updates etc.

  New support:
   - Support for AMD Versal Gen 2 DMA IP
   - Rcar RZ/G3S SoC dma controller
   - Support for Intel Diamond Rapids and Granite Rapids-D dma controllers
   - Support for Freescale ls1021a-qdma controller
   - New driver for Loongson-1 APB DMA
   - New driver for AMD QDMA
   - Pl08x in LPC32XX router dma driver

  Updates:
   - Support for dpdma cyclic dma mode
   - XML conversion for marvell xor dma bindings
   - Dma clocks documentation for imx dma"

* tag 'dmaengine-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (24 commits)
  dmaengine: loongson1-apb-dma: Fix the build warning caused by the size of pdev_irqname
  dmaengine: Fix spelling mistakes
  dmaengine: Add dma router for pl08x in LPC32XX SoC
  dmaengine: fsl-edma: add edma src ID check at request channel
  dmaengine: fsl-edma: change to guard(mutex) within fsl_edma3_xlate()
  dmaengine: avoid non-constant format string
  dmaengine: imx-dma: Remove i.MX21 support
  dt-bindings: dma: fsl,imx-dma: Document the DMA clocks
  dmaengine: Loongson1: Add Loongson-1 APB DMA driver
  dt-bindings: dma: Add Loongson-1 APB DMA
  dmaengine: zynqmp_dma: Add support for AMD Versal Gen 2 DMA IP
  dt-bindings: dmaengine: zynqmp_dma: Add a new compatible string
  dmaengine: idxd: Add new DSA and IAA device IDs for Diamond Rapids platform
  dmaengine: idxd: Add a new DSA device ID for Granite Rapids-D platform
  dmaengine: ti: k3-udma: Remove unused declarations
  dmaengine: amd: qdma: Add AMD QDMA driver
  dmaengine: xilinx: dpdma: Add support for cyclic dma mode
  dma: ipu: Remove include/linux/dma/ipu-dma.h
  dt-bindings: dma: fsl-mxs-dma: Add compatible string "fsl,imx8qxp-dma-apbh"
  dt-bindings: fsl-qdma: allow compatible string fallback to fsl,ls1021a-qdma
  ...
2024-09-23 14:08:08 -07:00
Piotr Wojtaszczyk
def1baeb25 dt-bindings: dma: Add lpc32xx DMA mux binding
LPC32XX SoCs use pl080 dma controller which have few request signals
multiplexed between peripherals. This binding describes how devices can
use the multiplexed request signals.

Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240627150046.258795-3-piotr.wojtaszczyk@timesys.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2024-09-13 14:01:34 -05:00
Yu-Chun Lin
a7fcc23274 dt-bindings: Fix various typos
Corrected several typos in Documentation/devicetree/bindings files.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Yu-Chun Lin <eleanor15x@gmail.com>
Link: https://lore.kernel.org/r/20240905151943.2792056-1-eleanor15x@gmail.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2024-09-13 14:01:34 -05:00
Nikita Shubin
581e2ff84f dt-bindings: dma: Add Cirrus EP93xx
Add YAML bindings for ep93xx SoC DMA.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-12 14:33:10 +00:00
Fabio Estevam
2ccf482268 dt-bindings: dma: fsl,imx-dma: Document the DMA clocks
Document the IPG and AHB clocks that are needed by the DMA hardware
as required properties.

It is not possible to have DMA functional without the DMA clocks
being turned on.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240807170517.64290-1-festevam@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-29 22:48:47 +05:30
Keguang Zhang
7ea270bb93 dt-bindings: dma: Add Loongson-1 APB DMA
Add devicetree binding document for Loongson-1 APB DMA.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
Link: https://lore.kernel.org/r/20240809-loongson1-dma-v12-1-d9469a4a6b85@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-29 22:47:24 +05:30
Abin Joseph
36545c6a68 dt-bindings: dmaengine: zynqmp_dma: Add a new compatible string
Add compatible string "amd,versal2-dma-1.0" to support AMD Versal Gen 2
platform.

AMD Versal Gen 2 has 8 LPD DMA IPs in PS that can be used as general
purpose DMAs which is designed to support memory to memory and memory to
IO buffer transfer. Versal Gen 2 DMA IP has different interrupt register
offset.

Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240808100024.317497-2-abin.joseph@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-29 22:46:16 +05:30
Frank Li
63556df6ac dt-bindings: dma: fsl-mxs-dma: Add compatible string "fsl,imx8qxp-dma-apbh"
Add compatible string "fsl,imx8qxp-dma-apbh". It requires power-domains
compared with "fsl,imx28-dma-apbh".

Allow 'power-domains' property because i.MX8DXL i.MX8QM and i.MX8QXP need
it.

Keep the same restriction about 'power-domains' for other compatible
strings.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240801214601.2620843-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-28 18:37:43 +05:30
Frank Li
0204485c5a dt-bindings: fsl-qdma: allow compatible string fallback to fsl,ls1021a-qdma
The IP of QDMA ls1028/ls1043/ls1046/ is same as ls1021. So allow compatible
string fallback to fsl,ls1021a-qdma.

The difference is that ls1021a-qdma have 3 irqs, and other have 5 irqs.

Fix below CHECK_DTB warning.
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: dma-controller@8380000: compatible: ['fsl,ls1046a-qdma', 'fsl,ls1021a-qdma'] is too long

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240710145400.2257718-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-05 23:02:35 +05:30
Shresth Prasad
31c70e0b7b dt-bindings: dma: mv-xor-v2: Convert to dtschema
Convert txt bindings of Marvell XOR v2 engines to dtschema to allow
for validation.

Also add missing property `dma-coherent` as `drivers/dma/mv_xor_v2.c`
calls various dma-coherent memory functions.

Signed-off-by: Shresth Prasad <shresthprasad7@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240723095518.9364-2-shresthprasad7@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-05 22:24:20 +05:30
Claudiu Beznea
7492b2f89c dt-bindings: dma: rz-dmac: Document RZ/G3S SoC
Document the Renesas RZ/G3S DMAC block. This is identical to the one found
on the RZ/G2L SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240711123405.2966302-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-05 22:15:22 +05:30
Linus Torvalds
7a46b17d4c Merge tag 'dmaengine-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
 "New support:

   - New dmaengine_prep_peripheral_dma_vec() to support transfers using
     dma vectors and documentation and user in AXI dma

   - STMicro STM32 DMA3 support and new capabilities of cyclic dma

  Updates:

   - Yaml conversion for Freescale imx dma and qdma bindings,
     sprd sc9860 dma binding

   - Altera msgdma updates for descriptor management"

* tag 'dmaengine-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (35 commits)
  dt-bindings: fsl-qdma: fix interrupts 'if' check logic
  dt-bindings: dma: sprd,sc9860-dma: convert to YAML
  dmaengine: fsl-dpaa2-qdma: add missing MODULE_DESCRIPTION() macro
  dmaengine: ti: add missing MODULE_DESCRIPTION() macros
  dmaengine: ti: cppi41: add missing MODULE_DESCRIPTION() macro
  dmaengine: virt-dma: add missing MODULE_DESCRIPTION() macro
  dmaengine: ti: k3-udma: Fix BCHAN count with UHC and HC channels
  dmaengine: sh: rz-dmac: Fix lockdep assert warning
  dmaengine: qcom: gpi: clean up the IRQ disable/enable in gpi_reset_chan()
  dmaengine: fsl-edma: change the memory access from local into remote mode in i.MX 8QM
  dmaengine: qcom: gpi: remove unused struct 'reg_info'
  dmaengine: moxart-dma: remove unused struct 'moxart_filter_data'
  dt-bindings: fsl-qdma: Convert to yaml format
  dmaengine: fsl-edma: remove redundant "idle" field from fsl_chan
  dmaengine: fsl-edma: request per-channel IRQ only when channel is allocated
  dmaengine: stm32-dma3: defer channel registration to specify channel name
  dmaengine: add channel device name to channel registration
  dmaengine: stm32-dma3: improve residue granularity
  dmaengine: stm32-dma3: add device_pause and device_resume ops
  dmaengine: stm32-dma3: add DMA_MEMCPY capability
  ...
2024-07-24 12:34:47 -07:00
Linus Torvalds
0ffb8a4c96 Merge tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Convert and add a bunch of IBM FSI related bindings

   - Add a new schema listing legacy compatibles which will (probably)
     never be documented. This will silence various checks warning about
     them.

   - Add bindings for Sierra Wireless mangOH Green SPI IoT interface,
     new Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75
     GPI DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and
     CSI-2 blocks

   - Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL
     q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema

   - Drop obsolete stericsson,abx500.txt

  DT core:

   - Update dtc to upstream version v1.7.0-93-g1df7b047fe43

   - Add support to run DT validation on DTs with applied overlays

   - Add helper for creating boolean properties in dynamic nodes and use
     that for dynamic PCI nodes

   - Clean-up early parsing of '#{address,size}-cells'"

* tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
  dt-bindings: timer: sprd-timer: convert to YAML
  dt-bindings: incomplete-devices: document devices without bindings
  dt-bindings: trivial-devices: document the Sierra Wireless mangOH Green SPI IoT interface
  scripts/dtc: Update to upstream version v1.7.0-93-g1df7b047fe43
  dt-bindings: soc: fsl: Add fsl,ls1028a-reset for reset syscon node
  dt-bindings: soc: fsl: cpm_qe: convert to yaml format
  dt-bindings: i2c: i2c-fsi: Convert to json-schema
  dt-bindings: fsi: Document the FSI Hub Controller
  dt-bindings: fsi: Document the AST2700 FSI controller
  dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
  dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
  dt-bindings: fsi: Document the FSI controller common properties
  dt-bindings: fsi: Document the IBM SBEFIFO engine
  dt-bindings: fsi: p9-occ: Convert to json-schema
  dt-bindings: fsi: Document the IBM SCOM engine
  dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
  dt-bindings: interrupt-controller: convert fsl,ls-scfg-msi to yaml
  dt-bindings: soc: fsl: Convert q(b)man-* to yaml format
  dt-bindings: misc: fsl,qoriq-mc: convert to yaml format
  dt-bindings: drop stale Anson Huang from maintainers
  ...
2024-07-17 18:07:31 -07:00
Frank Li
b8ec9dba02 dt-bindings: fsl-qdma: fix interrupts 'if' check logic
All compatible string include 'fsl,ls1021a-qdma'. Previous if check are
always true.

if:
  properties:
    compatible:
      contains:
       enum:
         - fsl,ls1021a-qdma

Change to check other compatible strings to get correct logic and fix
below CHECK_DTB warnings.

arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb:
dma-controller@8380000: interrupts: [[0, 43, 4], [0, 251, 4], [0, 252, 4], [0, 253, 4], [0, 254, 4]] is too long

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240701195717.1843041-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-10 15:42:40 +05:30