Matthew Auld
8e8e9c2663
drm/xe: unconditionally apply PINNED for pin_map()
...
Some users apply PINNED and some don't when using pin_map(). The pin in
pin_map() should imply PINNED so just unconditionally apply it and clean
up all users.
Signed-off-by: Matthew Auld <matthew.auld@intel.com >
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com >
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com >
Cc: Matthew Brost <matthew.brost@intel.com >
Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com >
Link: https://lore.kernel.org/r/20250403102440.266113-14-matthew.auld@intel.com
2025-04-04 11:41:08 +01:00
Piotr Piórkowski
cbc0a0ee34
drm/xe/pf: Use an explicit check to see if the device has LMTT
...
So far, the main condition for using LMTT has been to check that
the device is a discrete gfx.
Let's add a dedicated function to check if the device supports LMTT
as not all future discrete GPU platforms will require LMTT.
v2:
- use xe_has_device_lmtt only when necessary - leave IS_DGFX for other
things related to LMEM provisioning
v3:
- remove IS_SRIOV_PF condition from xe_device_has_lmtt (Michal
Wajdeczko)
- keep IS_SRIOV_PF asserts in LMTT-related code (Michal Wajdeczko)
v4:
- update commit description
Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com >
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com >
Cc: Michał Winiarski <michal.winiarski@intel.com >
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com >
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com >
Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com >
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20250207113111.853821-2-piotr.piorkowski@intel.com
2025-02-10 11:10:14 +01:00
Matt Roper
b4237bb4f5
drm/xe/lmtt: Convert register access to use xe_mmio
...
Stop using GT pointers for register access.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-60-matthew.d.roper@intel.com
2024-09-11 15:17:50 -07:00
Michal Wajdeczko
9790bbe3ba
drm/xe: Normalize NEEDS_64K BO flag
...
In commit 62742d1266michal.wajdeczko@intel.com >
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240715180538.1418-2-michal.wajdeczko@intel.com
2024-07-22 12:53:04 +02:00
Michal Wajdeczko
466a6c3855
drm/xe: Kill regs/xe_sriov_regs.h
...
There is no real benefit to maintain a separate file. The register
definitions related to SR-IOV can be placed in existing headers.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240702183704.1022-3-michal.wajdeczko@intel.com
2024-07-04 11:54:35 +02:00
Lucas De Marchi
62742d1266
drm/xe: Normalize bo flags macros
...
The flags stored in the BO grew over time without following
much a naming pattern. First of all, get rid of the _BIT suffix that was
banned from everywhere else due to the guideline in
drivers/gpu/drm/i915/i915_reg.h that xe kind of follows:
Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
Here the flags aren't for a register, but it's good practice to keep it
consistent.
Second divergence on names is the use or not of "CREATE". This is
because most of the flags are passed to xe_bo_create*() family of
functions, changing its behavior. However, since the flags are also
stored in the bo itself and checked elsewhere in the code, it seems
better to just omit the CREATE part.
With those 2 guidelines, all the flags are given the form
XE_BO_FLAG_<FLAG_NAME> with the following commands:
git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i \
-e "s/XE_BO_\([_A-Z0-9]*\)_BIT/XE_BO_\1/g" \
-e 's/XE_BO_CREATE_/XE_BO_FLAG_/g'
git grep -le "XE_BO_" -- drivers/gpu/drm/xe | xargs sed -i -r \
-e 's/XE_BO_(DEFER_BACKING|SCANOUT|FIXED_PLACEMENT|PAGETABLE|NEEDS_CPU_ACCESS|NEEDS_UC|INTERNAL_TEST|INTERNAL_64K|GGTT_INVALIDATE)/XE_BO_FLAG_\1/g'
And then the defines in drivers/gpu/drm/xe/xe_bo.h are adjusted to
follow the coding style.
Reviewed-by: Matthew Auld <matthew.auld@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240322142702.186529-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com >
2024-04-02 10:33:57 -07:00
Michal Wajdeczko
df26ac9464
drm/xe/pf: Always select Multi-Level LMTT for platforms 12.60+
...
The Multi-Level LMTT variant is not specific only to the PVC.
Change logic to select it for all new platforms beyond 12.60.
Bspec: 52404, 67468
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com >
Cc: Michał Winiarski <michal.winiarski@intel.com >
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240313104132.1045-4-michal.wajdeczko@intel.com
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com >
2024-03-15 22:20:52 +01:00
Michal Wajdeczko
28b2a21892
drm/xe/pf: Request 64K aligned allocations for LMTT PD
...
The LMTT Page Directory, as well as the directory entries, must be
aligned on a 64KB boundary in VRAM. Use explicit alignment flag to
match hardware requirement.
Bspec: 52404, 67468
Cc: Michał Winiarski <michal.winiarski@intel.com >
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240313104132.1045-3-michal.wajdeczko@intel.com
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com >
2024-03-15 22:20:52 +01:00
Michal Wajdeczko
f1a5d808b2
drm/xe/kunit: Add test for LMTT operations
...
The LMTT variants are abstracted with xe_lmtt_ops. Make sure that
both 2L and ML ops implementations are correct.
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com >
Link: https://lore.kernel.org/r/20231128151507.1015-6-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
2023-12-21 11:45:27 -05:00
Michal Wajdeczko
b1d2040582
drm/xe/pf: Introduce Local Memory Translation Table
...
The Local Memory Translation Table (LMTT) provides additional
abstraction for Virtual Functions (VF) accessing device VRAM.
This code is based on prior work of Michal Winiarski.
In this patch we focus only on LMTT initialization. Remaining LMTT
functions will be used once we add a VF provisioning to the PF.
Bspec: 44117, 52404, 59314
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com >
Link: https://lore.kernel.org/r/20231128151507.1015-4-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com >
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
2023-12-21 11:45:27 -05:00
