Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series
support both single and dual Cortex-A9 cores.
Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx.
They are different in implementation such as SMP, IPs integarted and
earlycon configure.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
ep107 was emulation platform and compatible string
have been changed long time ago.
"ARM: zynq: dts: split up device tree"
(sha1: e06f1a9ed7)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Merge "ARM: mach-bcm: dt updatees for 3.17" from Matt Porter:
- BCM Mobile SMP support
- BRCM STB platform support
* tag 'for-3.17/bcm-dt' of git://github.com/broadcom/mach-bcm:
ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
ARM: brcmstb: add misc. DT bindings for brcmstb
ARM: brcmstb: add CPU binding for Broadcom Brahma15
ARM: dts: enable SMP support for bcm21664
ARM: dts: enable SMP support for bcm28155
devicetree: bindings: document Broadcom CPU enable method
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Broadcom mobile SoCs use a ROM-implemented holding pen for
controlled boot of secondary cores. A special register is
used to communicate to the ROM that a secondary core should
start executing kernel code. This enable method is currently
used for members of the bcm281xx and bcm21664 SoC families.
The use of an enable method also allows the SMP operation vector to
be assigned as a result of device tree content for these SoCs.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Merge "Initial support for Rockchip RK3288 SoCs" from Heiko Stuebner:
* tag 'v3.17-rockchip-rk3288' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: Build dtbs for Rockchip boards
ARM: dts: add rk3288 evaluation board
ARM: dts: rockchip: add core rk3288 dtsi
ARM: rockchip: enable support for RK3288 SoCs
ARM: Kconfig: set default gpio number for rockchip SoCs
ARM: rockchip: add debug uart used by rk3288
ARM: rockchip: clarify usability of DEBUG_RK3X_UART debug_ll options
dt-bindings: arm: add cortex-a12 and cortex-a17 cpu compatible properties
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As announced parts from ARM they will probably be used in socs shortly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Jonathan writes:
Fourth round of IIO new drivers, functionality and cleanups for the 3.17 cycle
New functionality
* A new modifier to indicate that a rotation is relative to either
true or magnetic north. This is to be used by some magnetometers
that provide data in this way.
* hid magnetometer now supports output rotations from various variants on
North
* HMC5843 driver converted to regmap and reworked to allow easy support
of other similar devices. Support for HMC5983 added via both i2c and SPI.
* Rework of Exynos driver to simplify extension to support more devices.
* Addition of support for the Exynos3250 ADC (which requires an additional
clock) Support for quite a few more devices on its way.
Cleanups
* ad7997 - a number of cleanups and tweaks to how the events are controlled
to make it more intuitive.
* kxcjk - cleanups and minor fixes for this new driver.
Merge basic support for the Mediatek Cortex-A7 SoCs from Matthias Brugger:
Support is quite basic, as the only component working up to now are the
timers.
* tag 'v3.17-next-mediatek-support' of https://github.com/mbgg/linux-mediatek:
arm: mediatek: add dts for Aquaris5 mobile phone
dt-bindings: add documentation for Mediatek SoC
arm: add basic support for Mediatek MT6589 boards
Signed-off-by: Matthias Brugger matthias.bgg@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Driver providing perf backend for ARM Cache Coherent Network
interconnect. Supports counting all hardware events and crosspoint
watchpoints.
Currently works with CCN-504 only, although there should be
no changes required for CCN-508 (just impossible to test it now).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds a DT binding documentation for the MT6589 SoC from Mediatek.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Merge "ARM: mvebu: DT changes for v3.17 (round 2)" from Jason Cooper:
mvebu DT changes for v3.17 (round 2):
- kirkwood
* Add d2 Network v2 board
- mvebu
* Add Armada 375 ethernet node
* Add CA9 MPcore SoC controller node
* Add support for dynamic freq scaling on Armada XP
* tag 'mvebu-dt-3.17-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: update Armada XP DT for dynamic frequency scaling
ARM: mvebu: add CA9 MPcore SoC Controller node
ARM: mvebu: Enable the network controller in Armada 375 DB board
ARM: mvebu: Add support for the network controller in Armada 375 SoC
ARM: Kirkwood: add DT support for d2 Network v2
ARM: Kirkwood: allow to use netxbig DTSI for d2net_v2 DTS
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Samsung exynos cpuidle update for v3.17" from Kukjin Kim:
- add callbacks exynos_suspend() and exynos_powered_up()
for support cpuidle through mcpm
- skip exynos_cpuidle for exynos5420 because is uses
cpuidle-big-liggle generic cpuidle driver
- add generic functions to calculate cpu number is used
for pmu and this is required for exynos5420 multi-cluster
- add of_device_id structure for big.LITTLE cpuidle and
add "samsung,exynos5420" compatible string for exynos5420
* tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm
ARM: EXYNOS: do not allow cpuidle registration for exynos5420
cpuidle: big.LITTLE: init driver for exynos5420
cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config
ARM: EXYNOS: add generic function to calculate cpu number
cpuidle: big.LITTLE: add of_device_id structure
+ Linux 3.16-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: tegra: device tree changes for 3.17" from Thierry Reding:
- New board support:
* Apalis T30
- HDA support for Tegra124 and Venice2
- Display on Medcom Wide and Roth
- GK20A support on Tegra124
- XUSB pad controller for Tegra124 and Jetson TK1
- Various cleanups
This pulls in the for-3.17/fuse-move, for-3.17/dt-cros-ec-kbd and
for-3.17/xusb-padctl branches to resolve dependencies.
Note that the Apalis T30 support has a runtime dependency on the
for-3.17/pcie-regulators branch, so they should preferably be applied
in that order. I didn't merge that branch into this because Apalis T30
support is new, therefore can't regress, and because the dependency
exists only at runtime.
* tag 'tegra-for-3.17-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits)
ARM: tegra: roth: add display DT node
ARM: tegra: Fix typoed ams,ext-control properties
ARM: tegra: jetson-tk1: Add XUSB pad controller
ARM: tegra: tegra124: Add XUSB pad controller
ARM: tegra: add GK20A GPU to Tegra124 DT
ARM: tegra: of: add GK20A device tree binding
ARM: tegra: roth: enable input on mmc clock pins
ARM: tegra: roth: fix unsupported pinmux properties
ARM: tegra: Migrate Apalis T30 PCIe power supply scheme
ARM: tegra: tamonten: add the display to the Medcom Wide
ARM: tegra: tamonten: add the base board regulators
ARM: tegra: initial support for apalis t30
ARM: tegra: jetson-tk1: mark eMMC as non-removable
ARM: tegra: venice2 - Enable HDA
ARM: tegra: Add Tegra124 HDA support
ARM: tegra: Add the EC i2c tunnel to tegra124-venice2
soc/tegra: fuse: fix dummy functions
soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
soc/tegra: Add efuse and apbmisc bindings
soc/tegra: Add efuse driver for Tegra
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Xilinx Zynq changes for v3.17" from Michal Simek:
arm: Xilinx Zynq dt patches for v3.17
- Document and use new cadence serial binding
* tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: DT: Migrate UART to Cadence binding
tty: cadence: Document DT binding
+ Linux 3.16-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "omap dts changes for v3.17 merge window, part1" from Tony Lindgren:
First set of .dts changes for omaps for v3.17 merge window:
- Enable irqchip crossbar interrupt mapping. These changes
are based on an immutable irqchip branch set up by Jason
Cooper to make it easier to merge the related .dts changes.
- Removal of omap2 related static clock data that now comes
from device tree.
- Enabling of PHY regulators for various omaps
- Enabling of PCIe for dra7
- Add support for am437x starterkit
- Enable audio for for omap5
- Enable display and am335x-evmsk
* tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (43 commits)
ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040)
ARM: DTS: omap5-uevm: Add node for twl6040 audio codec
ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock
ARM: dts: dra7: Add dt data for PCIe controller
ARM: dts: dra7: Add dt data for PCIe PHY
ARM: dts: dra7: Add dt data for PCIe PHY control module
ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
ARM: dts: dra7-evm: Add regulator information to USB2 PHYs
ARM: omap2plus_defconfig: enable TPS65218 configs
ARM: dts: AM437x: Add TPS65218 device tree nodes
ARM: dts: AM437x: Fix i2c nodes indentation
ARM: dts: AM43x: Add TPS65218 device tree nodes
ARM: dts: Add devicetree for Gumstix Pepper board
ARM: dts: dra7: add crossbar device binding
ARM: dts: dra7: add routable-irqs property for gic node
ARM: OMAP24xx: clock: remove legacy clock data
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds the device tree to support Toradex Apalis T30, a
computer on module which can be used on different carrier boards.
The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L
RAM, eMMC, an LM95245 temperature sensor chip, an i210 resp. i211
gigabit Ethernet controller, an STMPE811 ADC/touch controller as well
as two MCP2515 CAN controllers. Furthermore, there is an SGTL5000 audio
codec which is not yet supported. Anything that is not self contained
on the module is disabled by default.
The device tree for the Evaluation Board includes the modules device
tree and enables the supported peripherals of the carrier board (the
Evaluation Board supports almost all of them).
While at it also add the device tree binding documentation for Apalis
T30.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[swarren: fixed some node sort orders]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.
Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
SPEAr SOCs have some miscellaneous registers which are used to configure
peripheral.
This patch adds dt node and binding information for this block.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: devicetree@vger.kernel.org
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
While powering on/off a local powerdomain in exynos5 chipsets, the
input clocks to each device gets modified. This behaviour is based
on the SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
(aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on
a domain everytime.
This patch adds the framework for getting the required mux and parent
clocks through a power domain device node. With this patch, while
powering off a domain, parent is set to oscclk and while powering back
on, its re-set to the correct parent which is as per the recommended
pd on/off sequence.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Documentation for atmel-pmc only list one compatible, add the remaining
compatible strings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Merge "Berlin DT changes for v3.17" from Sebastian Hesselbarth:
- L2CC latency properties for BG2Q
- DW i2c nodes for BG2Q and corresponding dev board
- SMP related nodes for BG2 and BG2Q
* tag 'berlin-dt-3.17-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: dts: berlin: add SMP related nodes and properties for BG2Q
ARM: dts: berlin: add SMP related nodes and properties for BG2
Documentation: bindings: add the marvell,berlin-smp CPU enable method
Documentation: bindings: add the Berlin CPU control doc
ARM: dts: berlin: enable i2c0 and i2c2
ARM: dts: berlin: add I2C nodes for BG2Q
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "DT IRQ and clock support for Versatile platforms" from Rob Herring.
This branch moves IRQ and clock support over to DT for the versatile
platforms.
* tag 'versatile-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
clk: versatile: add versatile OSC support
dts: versatile: add clock tree
ARM: timer-sp: allow getting timer1 clock from DT to fallback to legacy clock
dt/bindings: add compatible string for versatile osc clock
dt/bindings: arm-boards: add binding for Versatile core module
dts: versatile: add pl180 compatible strings
ARM: versatile: remove init_irq hook for DT boot
ARM: integrator: convert to use irqchip_init
irqchip: versatile-fpga: add support for arm,versatile-sic
irqchip: versatile-fpga: Add IRQCHIP_DECLARE support
dts: versatile: add missing irq controller properties
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131,
132, 133 are direct wired to hardware blocks bypassing crossbar.
This quirky implementation is *NOT* supposed to be the expectation
of crossbar hardware usage. However, these are already marked in our
description of the hardware with SKIP and RESERVED where appropriate.
Unfortunately, we need to be able to refer to these hardwired IRQs.
So, to request these, crossbar driver can use the existing information
from it's table that these SKIP/RESERVED maps are direct wired sources
and generic allocation/programming of crossbar should be avoided.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-17-git-send-email-r.sricharan@ti.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Currently we attempt to map any crossbar value to an IRQ, however,
this is not correct from hardware perspective. There is a max crossbar
event number upto which hardware supports. So describe the same in
device tree using 'ti,max-crossbar-sources' property and use it to
validate requests.
[ jac - remove MAX_SOURCES from binding doc, use integer because we
shouldn't put implementation details in the binding docs ]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-14-git-send-email-r.sricharan@ti.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since crossbar is s/w configurable, the initial settings of the
crossbar cannot be assumed to be sane. This implies that:
a) On initialization all un-reserved crossbars must be initialized to
a known 'safe' value.
b) When unmapping the interrupt, the safe value must be written to
ensure that the crossbar mapping matches with interrupt controller
usage.
So provide a safe value in the dt data to map if
'0' is not safe for the platform and use it during init and unmap
While at this, fix the below checkpatch warning.
Fixes checkpatch warning:
WARNING: Unnecessary space before function pointer arguments
#37: FILE: drivers/irqchip/irq-crossbar.c:37:
+ void (*write) (int, int);
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-5-git-send-email-r.sricharan@ti.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pull ARM fixes from Russell King:
"Another round of ARM fixes. The largest change here is the L2 changes
to work around problems for the Armada 37x/380 devices, where most of
the size comes down to comments rather than code.
The other significant fix here is for the ptrace code, to ensure that
rewritten syscalls work as intended. This was pointed out by Kees
Cook, but Will Deacon reworked the patch to be more elegant.
The remainder are fairly trivial changes"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8087/1: ptrace: reload syscall number after secure_computing() check
ARM: 8086/1: Set memblock limit for nommu
ARM: 8085/1: sa1100: collie: add top boot mtd partition
ARM: 8084/1: sa1100: collie: revert back to cfi_probe
ARM: 8080/1: mcpm.h: remove unused variable declaration
ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache
When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
skipped. Moreover, on some systems, it is harmful as it causes
deadlocks between the Marvell coherency mechanism, the Marvell PCIe
controller and the Cortex-A9.
To avoid this, this commit introduces a new Device Tree property
'arm,io-coherent' for the L2 cache controller node, valid only for the
PL310 cache. It identifies the usage of the PL310 cache in an I/O
coherent configuration. Internally, it makes the driver disable the
outer cache sync operation.
Note that technically speaking, a fully coherent system wouldn't
require any of the other .outer_cache operations. However, in
practice, when booting secondary CPUs, these are not yet coherent, and
therefore a set of cache maintenance operations are necessary at this
point. This explains why we keep the other .outer_cache operations and
only ->sync is disabled.
While in theory any write to a PL310 register could cause the
deadlock, in practice, disabling ->sync is sufficient to workaround
the deadlock, since the other cache maintenance operations are only
used in very specific situations.
Contrary to previous versions of this patch, this new version does not
simply NULL-ify the ->sync member, because the l2c_init_data
structures are now 'const' and therefore cannot be modified, which is
a good thing. Therefore, this patch introduces a separate
l2c_init_data instance, called of_l2c310_coherent_data.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Pull hwmon fixes from Guenter Roeck:
"Various minor fixes"
* tag 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging:
hwmon: (gpio-fan) Change name used in hwmon_device_register_with_groups
hwmon: (emc1403) Fix missing 'select REGMAP_I2C' in Kconfig
hwmon: (ntc_thermistor) Use the manufacturer name properly
devicetree: bindings: Document murata vendor prefix
hwmon: (w83l786ng) Report correct minimum fan speed
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based Thermistors.
But, the driver extensively uses "NTC" as the vendor name.
This patch corrects the vendor name also updates the
compatibility strings according to the vendor-prefix.txt
Note: Drivers continue to support the previous compatible strings
but further addition of these compatible strings in device tree
is deprecated.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
