Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add the l4_sys_free_clk node
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock
which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk
passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided
node and makes the sdmmc_clk it's parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: renamed ciu_clk to sdmmc_clk_divided
Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc
as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus
we will need to have 2 separate board files, one for SDMMC and one for
QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi
so that we use common peripherals for each flavor of the devkits.
Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Arria10 devkit is using UART1 for the debug uart port. Remove
unused aliases.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add removal of unused aliases
Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart
nodes should be enabled in the appropriate board file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Si5351 clock generator on CuBox uses XTAL as clock reference, name the
clock phandle accordingly.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With reworked device tree files for Compulab CM-A510 SoM and SBC-A510
base board, now add the correspoding board file to Makefile again.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Existing dts file for Compulab CM-A510 was very limited due to missing
hardware. Now that we actually found somebody with that board, properly
rework it to provide a CoM/SoM include and a board file for Compulab's
SBC-A510.
Both the CM-A510 SoM and the SBC-A510 can be configured with different
options, so we only enable a minimum set of options. The actual board
configuration will have to be set by either the bootloader or user.
Although functionally not required, repeat even disabled nodes again
to increse their visibility in the dtsi/dts files.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Gabriel Dobato <dobatog@gmail.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This adds a i2c-mux-pinctrl node to dove.dtsi for the internal i2c
mux found on Dove SoCs. Up to now, we had no board using any of the
two additional i2c busses, so make sure the change does not break
any existing boards.
Therefore, we rename the i2c-controller node label to "i2c" and
enable it by default. Also, the dedicated sub-bus (now "i2c0") is
enabled by default. The two optional sub-busses require additional
external pin-muxing, so disable them by default.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The clock-frequency property became obsolete since the rework of the main
clock driver in 3.16 (see commit 27cb1c2083).
It now get and uses the clock-frequency from the main_xtal node.
Signed-off-by: Gaël PORTAY <g.portay@overkiz.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The Integrators and the RealView use simple MFD devices with register bit
LEDs as subnodes, update these to use the "simple-mfd" compatible property
so that subdevices get spawned from the MFD nexi.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Note that from now on any of the pfc8575 gpio keys will wake up the
system, as the pfc8575 cannot mask individual interrupts.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Spansion s25fl512s is compatible with "nor-jedec". Hence add the
"nor-jedec" compatible value, so the driver can bind against the generic
name, cfr. commit 8ff16cf77c ("Documentation: devicetree: m25p80:
add "nor-jedec" binding").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Spansion s25fl008k is compatible with "nor-jedec". Hence add the
"nor-jedec" compatible value, so the driver can bind against the generic
name, cfr. commit 8ff16cf77c ("Documentation: devicetree: m25p80:
add "nor-jedec" binding").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Spansion s25fl512s is compatible with "nor-jedec". Hence add the
"nor-jedec" compatible value, so the driver can bind against the generic
name, cfr. commit 8ff16cf77c ("Documentation: devicetree: m25p80:
add "nor-jedec" binding").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Spansion s25fl008k is compatible with "nor-jedec". Hence add the
"nor-jedec" compatible value, so the driver can bind against the generic
name, cfr. commit 8ff16cf77c ("Documentation: devicetree: m25p80:
add "nor-jedec" binding").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Spansion s25fl512s is compatible with "nor-jedec". Hence add the
"nor-jedec" compatible value, so the driver can bind against the generic
name, cfr. commit 8ff16cf77c ("Documentation: devicetree: m25p80:
add "nor-jedec" binding").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the external IRQ controllers irqc0 and irqc1 to the IRQC module
clock, so they can be power managed using that clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[horms: corrected typo in changelog to refer to r8a73a4]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Pull samsung fixes from Kukjin Kim:
"Here is Samsung fixes for v4.1. Since I've missed to send this via
arm-soc tree before v4.1-rc3, so I'm sending this to you directly
- fix commit ea08de16eb ("ARM: dts: Add DISP1 power domain for
exynos5420") which causes 'unhandled fault: imprecise external
abort' error when PD turned off. ("make DP a consumer of DISP1
power domain")
- fix 's3c-rtc' probe failure on Odriod-X2/U2/U3 boards ("add
'rtc_src' clock to rtc node for source clock of rtc")
- fix typo for 'cpu-crit-0' trip point on exynos5420/5440
- fix S2R failure on exynos5250-snow due to card power of Marvell
WiFi driver (suspend/resume) ("add keep-power-in-susped to WiFi
SDIO node")"
* tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Add keep-power-in-suspend to WiFi SDIO node for exynos5250-snow
ARM: dts: Fix typo in trip point temperature for exynos5420/5440
ARM: dts: add 'rtc_src' clock to rtc node for exynos4412-odroid boards
ARM: dts: Make DP a consumer of DISP1 power domain on Exynos5420
The pinctrl groups for SPI until now were also adding the chip selects in
the SPI pinctrl group.
This was causing a few issues, since a board was forced to use a random
number of chipselects, even though it might use one of these chip selects
for another pin.
The number of chipselects defined was also not the same from one group to
another because of different needs at the time these groups have been
introduced, resulting in no clear view from the board DTS on what exactly
is being muxed, which even might change in the future.
Solve this by creating different pinctrl groups for the chipselects and the
standard SPI pins (CLK, MOSI and MISO) so that we fix both issues.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A few lines (probably copy pasted) have an indentation mixing tabs and
spaces that triggers a checkpatch warning.
Fix those, and while we're at it, fix the space-indented sections.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A few lines in our DTSIs are over the 80 characters limit, making
checkpatch complain about that.
If possible (and relevant), wrap these lines to 80 characters.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
