Marvell Berlin BG2 based Sony NSZ-GS7 has an unpopulated SATA plug
on its PCB solder side. As it is quite easy to populate and I have
done it, enable AHCI and SATA by default.
Acked-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The apb2 clocks are actually the same as apb1 clocks on the other sunxi
platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk".
Update the dtsi to use the new unified apb1 clk.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
With the new factors infrastructure in place, we can unify apb1 and
apb1_mux as a single clock now.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
[wens@csie.org: Change apb1 node label to "apb1"; reword commit title]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
by adding labels to DWC3 nodes, it's far easier
for boards to reference them.
Signed-off-by: Felipe Balbi <balbi@ti.com>
[tony@atomide.com: updated for otg 4 move to dra74x.dtsi]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Whenever Suspend PHY bit is set on AM437x devices,
USB will not work due to Set EP Configuration command
always failing.
This was only found after a recent commit 2164a47 (usb:
dwc3: set SUSPHY bit for all cores, which will be merged
for v3.19) added a missing *required* step to dwc3
initialization. Synopsys Databook requires that we enable
Suspend PHY bit after initialization but that, unfortunately,
breaks AM437x.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7 Data Manual (SPRS857L - August 2014) section 4.1.1 states: "All
unused power supply balls must be supplied with the voltages specified
in the Section 5.2, Recommended Operating Conditions".
This implies that all unused voltage rails for Vayu can never be
switched off even if the hardware blocks inside that voltage domain is
unused. Switching off these unused rails may result in stability issues
on other domains and increased leakage and power-on-hour impacts.
J6eco-evm dts file already considers this, however j6evm-dts file needs
to be fixed to consider this constraint of the SoC.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add MMC1 and 2 nodes. MMC1 is SDcard and MMC2 is eMMC.
NOTE on MMC1 card detect: Ideally, we should be using in-built SDCD
support, but we dont have it yet. So, use the fact that control module
of DRA7 is setup such that no matter what mode one configures it, GPIO
option is always hardwired in - use GPIO mode for SDcard detection.
[peter.ujfalusi@ti.com]
The power line feeding the SD card is also used by other devices on the EVM.
Use generic name instead of mmc2_3v3 so when other devices want to use the
same regulator it will look a bit better.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With Commit adff5962fd ("Input: introduce palmas-pwrbutton"), we can
now support tps power button as a event source - This is SW7 (PB/WAKE)
on the J6-evm.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Even thought sys_nirq1 is hardwired on the SoC for the pin, it is
better to configure the pin to the required mux configuration.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The ldo4_reg regulator provides power to the USB1 and USB2
High Speed PHYs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The 4th USB controller instance present only on the DRA74x family of
devices so move it there.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA72-evm has a 256MB 16-bit wide NAND chip. Add
pinmux and NAND node.
The NAND chips 'Chip select' and 'Write protect' can be
controlled using DIP Switch SW5. To use NAND,
the switch must be configured like so:
SW5.1 (NAND_SELn) = ON (LOW)
SW5.9 (GPMC_WPN) = OFF (HIGH)
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use omap specific pinctrl defines (OMAP3_CORE1_IOPAD) to configure
the padconf register offset.
Signed-off-by: Marek Belisko <marek@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add DSS related pinmux and display data nodes required to support
DVI video out on SBC-T3530, SBC-T3730 and SBC-T3517.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DCDC3 supplies voltage to DDR. Fix DCDC3 volatge to 1.5V which is the reset
value. Programming to a non-reset value while executing from DDR will result
in random hangs.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DCDC3 supplies voltage to DDR. Fix DCDC3 volatge to 1.5V which is the reset
value. Programming to a non-reset value while executing from DDR will result
in random hangs.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DCDC3 supplies voltage to DDR. Fix DCDC3 volatge to 1.5V which is the reset
value. Programming to a non-reset value while executing from DDR will result
in random hangs.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the interrupts property to all the 13 mailbox nodes in
DRA7xx. The interrupts property information added is inline
with the expected values with the DRA7xx crossbar driver,
and is common to both DRA74x and DRA72x SoCs.
Do note that the mailbox 1 is only capable of generating out
3 interrupts, while all the remaining mailboxes have 4
interrupts each.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
According to the datasheet, the operating clock for IIC0 is the HPP
(RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
speed (50 Mhz).
This is consistent with IIC0 being located in the A4R PM domain, and
IIC1 in the A3SP PM domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Merge "Nomadik updates for the v3.19 series" from Linus Walleij:
Nomadik changes for the v3.19 development series:
- Rearrange the DTS files to make a pure SoC-specific file and
a pure board file for S8815.
- Add the device tree for the NDK15 board.
- Update the defconfig and configure in the STMPE expander by
default on the Nomadik.
* tag 'nomadik-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: configure in STMPE support
ARM: update Nomadik config
ARM: nomadik: device tree for NHK15 board
ARM: nomadik: push ethernet down to board
ARM: nomadik: set up MCDATDIR2
ARM: nomadik: move GPIO I2C to S8815 board file
ARM: nomadik: disable chrystals in top level board files
ARM: nomadik: move MMC/SD card detect GPIO to board DTS
Signed-off-by: Olof Johansson <olof@lixom.net>
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "at91: dt for 3.19 #1" from Nicolas Ferre:
"Very little DT update for AT91. More will come but I want to send this first
batch soon so it doesn't get in the way of larger modifications."
First DT batch for 3.19:
- CAN device nodes for at91sam9263 and at91sam9x5
- at91sam9x5 DMA definitions for usart
* tag 'at91-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91/dt: at91sam9263: Add CAN device nodes
ARM: at91/dt: at91sam9x5: Add CAN device nodes
ARM: at91/dt/trivial: at91sam9x5_can.dtsi: comment and whitespace fixes
ARM: at91: at91sam9x5 dt: add usart dma definitions to dt
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Ux500 core changes for v3.19" from Linus Walleij:
"please pull in these Ux500 core changes for this kernel development
cycle: mainly a generic power domain implementation from Ulf Hansson
that needs to get queued up in -next and tested."
Generic power domains for the Ux500
* tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: Add i2c devices to the VAPE PM domain
ARM: ux500: Add spi and ssp devices to the VAPE PM domain
ARM: ux500: Add sdi devices to the VAPE PM domain
ARM: ux500: Add DT node for ux500 PM domains
ARM: ux500: Enable Kconfig for the generic PM domain
ARM: ux500: Initial support for PM domains
dt: bindings: ux500: Add header for PM domains specifiers
dt: bindings: ux500: Add documentation for PM domains
ARM: u300: Convert pr_warning to pr_warn
Merge "ARM: berlin: DT changes for v3.19 (round 1)" from Sebastian Hesselbarth:
"This is Berlin DT changes for v3.19 and contains those patches that missed
the v3.18 merge window plus corresponding patches to catch-up with Antoine's
BG2Q improvements for BG2 and BG2CD. We now have working SDHCI and Ethernet
on all SoCs (well, BG2CD has HDMI HEC only), SATA PHY support for BG2 is still
pending."
Berlin DT changes for v3.19 (round 1)
- AHCI and SATA PHY nodes for BG2Q
- Reset controller binding docs
- Ethernet nodes for BG2, BG2CD
- SDHCI nodes for BG2, BG2CD
- Corresponding board changes to enable AHCI, Ethernet, SDHCI
* tag 'berlin-dt-3.19-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: dts: berlin: Enable eMMC on Sony NSZ-GS7
ARM: dts: berlin: Enable WiFi on Google Chromecast
ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD
ARM: dts: berlin: Enable ethernet on Sony NSZ-GS7
ARM: dts: berlin: Add phy-connection-type to BG2Q Ethernet
ARM: dts: berlin: Add BG2CD ethernet DT nodes
ARM: dts: berlin: Add BG2 ethernet DT nodes
ARM: dts: berlin: Add GPIO leds to Google Chromecast
ARM: dts: berlin: enable timer 1 for sched_clock
ARM: dts: berlin: add a required reset property in the chip controller node
Documentation: bindings: add reset bindings docs for Marvell Berlin SoCs
ARM: dts: berlin: enable the eSATA interface on the BG2Q DMP
ARM: dts: berlin: add the AHCI node for the BG2Q
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Broadcom Cygnus SoC Device Tree changes" from Florian Fianelli:
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.
These are the Device Tree changes
* tag 'arm-soc/for-3.18/cygnus-dts-v9' of http://github.com/brcm/linux:
ARM: dts: Enable Broadcom Cygnus SoC
dt-bindings: Document Broadcom Cygnus SoC and clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
The dma controller requires that the ahb1 bus clock be driven by pll6
for peripheral access to work. Previously this was done in the dma
controller driver, but was since removed as part of a series to unify
the ahb1_mux and ahb1 clock drivers, in
14e0e28 dmaengine: sun6i: Remove obsolete clk muxing code
Unfortunately the rest of that series did not make it, leaving us with
broken dma on sun6i.
This patch reparents ahb1_mux to pll6 using the DT assigned-clocks
properties in the dma controller node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Support for the 2 PTMs, 3 ETMs, funnel, TPIU and replicator
connected to the ETB are included. Proper handling of the
ITM and the replicator linked to it along with the CTIs
and SWO are not included.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
