GPIO modules are also interrupt sources. However, they require both the
GPIO number and IRQ type to function properly.
By declaring that GPIO uses interrupt-cells=<1>, we essentially do not
allow users of the nodes to use the interrupt property appropritely.
With this change, the following now works:
interrupt-parent = <&gpio6>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
Fixes: 6e58b8f1da ('ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board')
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For v3.14 and prior, 1-bit Hamming code ECC via software was used
for NAND on this board.
Commit c06c527016 in v3.15 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.
This ECC layout change causes NAND filesystems created in v3.14
and prior to be unusable in v3.15 and later. So revert back to
using software ECC scheme.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Hummingboard has no over current hardware, so disable the over current
detection for both ports.
Cubox-i has over current hardware, so appropriately configure this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
On r8a7791, i2c6 (aka iic3) doesn't need pinmux, but the koelsch dts
refers to non-existent pinmux configuration data:
pinmux core: sh-pfc does not support function i2c6
sh-pfc e6060000.pfc: invalid function i2c6 in map table
Remove it to fix this.
Fixes: commit 1d41f36a68 ("ARM: shmobile:
koelsch dts: Add VDD MPU regulator for DVFS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Olof Johansson <olof@lixom.net>
Working on Gigabit/PCIe support in U-Boot for Apalis T30 I realised
that the current device tree source includes for our modules only
happen to work due to referencing the on-carrier 5v0 supply from USB
which is not at all available on-module. The modules actually contain
TPS60150 charge pumps to generate the PMIC required 5 volts from the
one and only 3.3 volt module supply. This patch fixes this.
(Note: When back-porting this to v3.16 stable releases, simply drop the
change to tegra30-apalis.dtsi; that file was added in v3.17)
Cc: <stable@vger.kernel.org> #v3.16+
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: rockchip: fix for 3.17" from Heiko Stubner:
Pinctrl that got accidentially dropped when reorganizing the
dts files and addition of the new Rockchip list to MAINTAINERS.
* tag 'v3.17-rockchip-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
MAINTAINERS: add new Rockchip SoC list
ARM: dts: rockchip: readd missing mmc0 pinctrl settings
Signed-off-by: Olof Johansson <olof@lixom.net>
During the restructuring of the Rockchip Cortex-A9 dtsi files it seems
like the pinctrl settings vanished at some point from the mmc0 support.
This of course renders them unusable, so readd the necessary pinctrl
properties.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the CMT1 counters to the r8a7740 device tree and make it
disabled by default.
Based on work by Magnus Damm.
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Merge "Allwinner DT changes, take 2" from Maxime Ripard:
Only a single patch in here that fixes a DTC warning.
* tag 'sunxi-dt-for-3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Add an "interrupt-parent = <&gic>;" at the top, which is inherited by
all child nodes, so the "interrupt-parent" properties can be removed
from the individual child nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's already an "interrupt-parent = <&gic>;" at the top, which is
inherited by all child nodes, so the "interrupt-parent" property in
the sound node can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's already an "interrupt-parent = <&gic>;" at the top, which is
inherited by all child nodes, so the "interrupt-parent" property in
the sound node can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's already an "interrupt-parent = <&gic>;" at the top, which is
inherited by all child nodes, so the "interrupt-parent" properties in
the serial nodes can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add CPU Frequency information to the r8a7778 DTS file. This
will allow us to use the shared C code on r8a7778 and BockW
which reads out the clock frequency from DT and calculates the
delay settings from there.
Also add other missing CPU information to the r8a7778 DTS.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add CPU Frequency information to the sh73a0 DTS file. This
will allow us to use the shared C code on sh73a0 and KZM9G
which reads out the clock frequency from DT and calculates the
delay settings from there.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add CPU Frequency information to the sh7372 DTS file. This
will allow us to use the shared C code on sh7372 and Mackerel
which reads out the clock frequency from DT and calculates the
delay settings from there.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add basic IPQ8064 SoC include device tree and support for basic booting on
the AP148 Reference board with support for UART, I2C, and SPI.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the necessary DT node to probe the serial driver on
APQ8084 platforms.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the necessary node to probe the global clock
controller on APQ8084 platforms.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Increase max i2c bus frequency beyond the default for faster
data transfers. According to the manual, these faster speeds are
only available when the board is wired up the right way. In this case,
the vendor kernel has run at this speed for a long time.
sda-delay is needed for talking to RTC on PMIC, otherwise the i2c
controller never sees an ACK. Strangely the other PMIC i2c slave (the
main one) works fine even without this delay. I Chose value 100 to
match the vendor kernel.
Signed-off-by: Daniel Drake <drake@endlessm.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The ODROID kernel shows that the PMIC interrupt line is hooked up
to pin GPX3-2.
This is needed for the max77686-irq driver to create the PMIC IRQ
domain, which is needed by max77686-rtc.
Signed-off-by: Daniel Drake <drake@endlessm.com>
Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Pull AT91 ramc and reset/poweroff related DT patches from Maxim Ripard:
"This branch gathers a few devicetree patches needed for the reworks found in
the later patches to be sent. More precisely, it holds:
- The addition of ddrck for the sama5d3 and the sam9 SoCs
- The addition of the shutdown controller node in the sama5d3 DTSI
- The slight rework of the ramc bindings for the SoCs that have several RAM
controllers"
Conflicts:
arch/arm/boot/dts/at91sam9g45.dtsi
The current pinfunc define all uart CTS_B IO port for DCE uart 'CTS_B'
IP port. Since uart IP port 'CTS_B' is output, and it don't need to
set 'SELECT_INPUT' bit.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The DeviceTree files for the Peach Pit and Pi machines have
a simplistic model of the connections between the different
regulators since not all the tps65090 regulators get their
input supply voltage from the VDC. DCDC1-3, LD0-1 and fet7
parent supply is indded VDC but the fet1-6 get their input
supply from the DCDC1 and DCDC2 output voltage rails.
Update the DeviceTree to better reflect the real connections
between tps65090 regulators. Having this information in the
DTS is useful since FETs are switches that don't provide an
output voltage so the regulator core needs to fetch the FET
parent output voltage if the child voltage is queried.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And "supports-highspeed" property in dw-mmc is deprecated.
"supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tushar Behera <trblinux@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Sachin Kamat <sachin.kamat@samsung.com>
[kgene.kim@samsung.com: rebased exynos5250-snow changes]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
exynos5250-cros-common.dtsi was meant for sharing common pieces across
ChromeOS devices. This turned out premature, as several devices ended up
in the common file that are not common after all. Since the remaining
common ChromeOS pieces are fairly minor, exynos5250-cros-common.dtsi
was requested to be merged into the Snow device tree, sharing only the
keyboard controller for now. This may be re-evaluated as both mature.
Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The clock-frequency values of the i2c controller nodes match the
defaults of the driver. Remove the properties to use the defaults,
and be consistent with sun8i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
i2c0 is connected to the gsl1680 capacitive touch panel controller.
i2c1 is connected to an mma7660 3-axis accelerometer.
i2c2 is connected to the front and back gc0309 camera sensors.
The camera sensors require additional regulators be enabled before
they are available.
All these peripherals are not supported by the kernel yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add nodes for the 3 i2c controllers found on A23 SoCs to the sun8i DTSI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Increase max i2c bus frequency beyond the default for faster
data transfers. According to the manual, these faster speeds are
only available when the board is wired up the right way. In this case,
the vendor kernel has run at this speed for a long time.
sda-delay is needed for talking to RTC on PMIC, otherwise the i2c
controller never sees an ACK. Strangely the other PMIC i2c slave (the
main one) works fine even without this delay. I Chose value 100 to
match the vendor kernel.
Signed-off-by: Daniel Drake <drake@endlessm.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The ODROID kernel shows that the PMIC interrupt line is hooked up
to pin GPX3-2.
This is needed for the max77686-irq driver to create the PMIC IRQ
domain, which is needed by max77686-rtc.
Signed-off-by: Daniel Drake <drake@endlessm.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Previous version had an extra 'fsl' which made the pins not match
any entry. The console message,
vf610-pinctrl 40048000.iomuxc: no fsl,pins property in node \
/soc/aips-bus@40000000/iomuxc@40048000/vf610-twr/esdhc1grp
is displayed without the fix. The prior version would generally
work as u-boot sets the pins properly for sdhc. This change allows
Linux sdhc use even if u-boot is built without sdhc support.
Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Fixes: 0517fe6aa8 ("ARM: dts: vf610-twr: Add support for sdhc1")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
